Semiconductor device and its manufacturing method

ABSTRACT

The present invention relates to a semiconductor device in which a capacitance element is mounted on a semiconductor substrate as well as a method of fabricating the device. According to the present invention, a substantial lower electrode is formed on a semiconductor substrate through a first insulation film; a peripheral electrode, i.e. the periphery of the lower electrode or a dummy electrode, which has the surface higher than the surface of the lower electrode being formed integrally with or separately from the lower electrode; an upper electrode being formed on the lower electrode through a dielectric film; a capacitance element being formed so that at least the surface of the dielectric film may lie on a level lower than the surface of the peripheral electrode; and a recess surrounded by the peripheral electrode being filled with a smoothing film. 
     As a result, when the smoothing film is formed, at least the dielectric film does not sustain damage and so a capacitance element having less fluctuation in its characteristics and high reliability can be obtained.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and itsfabricating method. Particularly, it relates to a semiconductor devicein which a capacitance element is mounted on a semiconductor substrateand a method of fabricating the device.

BACKGROUND ART

A conventional process for fabricating LSI (Large-scale IntegratedCircuit) where a capacitance element is formed on a semiconductorsubstrate will be described with reference to schematic sectionalprocess diagrams of FIG. 39 to FIG. 41.

To start with, as shown in FIG. 39, a first insulation film 12 and asecond insulation film 16 which are made of SiO₂ film or the like arepiled in turn on a semiconductor substrate 10.

Subsequently, using the sputtering method for example, on the secondinsulation film 16 are piled a Ti layer, a TiON layer, a Ti layer, anAl—Si layer and a TiN layer in turn from below to form aTiN/Al—Si/Ti/TiON/Ti lamination film.

Subsequently, using CVD (Chemical Vapor Deposition) method for example,on the TiN/Al—Si/Ti/TiON/Ti lamination film is piled a dielectric filmof SiO₂, SiN, Ta₂O₅ and the like. Further, using the sputtering methodfor example, on the dielectric film is piled a conductor layer of a Tilayer, a TiN layer or the like.

Then, through the photolithographing process and RIT (Reactive IonEtching) process, these piled conductor layer and dielectric film areselectively removed by etching into a predetermined pattern to form anupper electrode 22 of Ti, TiN and the like on the TiN/Al—Si/Ti/TiON/Tilamination film through a dielectric film 20 of SiO₂ SiN, Ta₂O₅ or thelike.

Subsequently, through the photolithographing process and RIE process,the TiN/Al—Si/Ti/TiON/Ti lamination film 18 is selectively removed byetching into a predetermined pattern to form a lower electrode 18 d ofthe TiN/Al—Si/Ti/TiON/Ti lamination film.

In this way, a capacitance element comprised of the upper electrode 22and the lower electrode 18 d which sandwich the dielectric film 20between them is formed.

Subsequently, using the plasma CVD method for example, which uses TEOS(tetraethoxy silane; Si(OC₂H₅)₄) as raw materials, a SiO₂ film is piledon the whole surface of a base body including the upper electrode 22 andlower electrode 18 d. After the SiO₂ film is further coated with SOG(Spin On Glass) film, a smoothing process that etches back these SOGfilm and SiO₂ film is performed. In other words, unevenness of thesurface of the base body is smoothed by filling with a smoothinginsulation film 24 formed of the SiO₂ film and SOG film.

Note that, on this occasion, because the surface of the upper electrode22 formed on the lower electrode 18 d lies on a higher level than thesurface of the lower electrode 22, the surface of the upper electrodemay have sometimes been in a exposed state.

Next, as shown in FIG. 40, using the plasma CVD method for example, aninsulation film 26 made of, e.g. SiO₂ film is piled on the whole surfaceof the base body including the upper electrode 22 and the smoothinginsulation film 24. An inter-layer insulation film 27 is thus formed bythe smoothing insulation film 24 and insulation film 26.

Subsequently, using the photolithographing process and the dry etchingmethod, the inter-layer insulation film 27 on the upper electrode 22 isselectively removed by etching and the inter-layer insulation film 27 onthe lower electrode 18 d is also selectively removed by etching to opena first via-hole 28 d and a second via-hole 28 e. At this time, in orderto reduce a contact resistance, TiN in the surface of the lowerelectrode 18 d may sometimes be removed.

Next, as shown in FIG. 41, after an Al-alloy layer is piled on the wholesurface of the base body using the sputtering method for example, theAl-alloy layer is processed using the photolithographing process and thedry etching method to form a first Al-alloy upper layer wiring layer 30d and a second Al-alloy upper layer wiring layer 30 e that are connectedto the upper electrode 22 and the lower electrode 18 d through the firstand second via-holes 28 d and 28 e, respectively.

However, in the conventional process of forming a capacitance element,when the smoothing process to smooth unevenness of the surface of thebase body by filling with the smoothing insulation film 24 formed of theSiO₂ film and SOG film is performed after a capacitance elementcomprised of the upper electrode 22 and lower electrode 18 d thatsandwich the dielectric film 20 between them is formed, because thesurface of the upper electrode 22 formed on the lower electrode 18 dlies on a higher level than the surface of lower electrode 18 d, theupper electrode 22 and further, even the dielectric film 20 lyingthereunder is subjected to etching by the etch-back in the smoothingprocess. That is to say, in the smoothing process, the upper electrode22 and further the dielectric film 20 lying thereunder sustain damage.

Therefore, there is a problem in which characteristics of a capacitanceelement such as a capacitance value fluctuate or its reliabilitydeteriorates, so that it is impossible to obtain such a capacitanceelement that has satisfactory characteristics and high reliability.

Moreover, when the first and second via-holes 28 d and 28 e are openedso as to form the first and second Al-alloy upper layer wiring layers 30d and 30 e connected respectively to the upper electrode 22 and lowerelectrode 18 d of a capacitance element, the film thickness ofinter-layer insulation film 27 on the upper electrode 22 to be etchedfor opening the first via-hole 28 d is thicker than the film thicknessof inter-layer insulation film 27 on the lower electrode 18 d to beetched for opening the second via-hole 28 e. Thus, when the first andsecond via-holes 28 d and 28 e are both intended to be openedsatisfactorily, excess over-etching on the surface of upper electrode 22will inevitably take place. As a result, the upper electrode 22 or thedielectric film 20 lying thereunder will sustain damage due to theover-etching.

Consequently, this point also raises the problem in which thecharacteristics of capacitance element such as a capacitance valuefluctuate or its reliability deteriorates, thus making it impossible toobtain such a capacitance element that has satisfactory characteristicsand high reliability.

Furthermore, the following problem is also raised.

That is, in a conventional capacitance element, when comparison is madebetween distances from an area where the upper electrode 22 and lowerelectrode 18 d are opposed to each other, which effectively functions asa capacitance element, to the first Al-alloy upper layer wiring layer 30d and to the second Al-alloy upper layer wiring layer 30 e, the distanceon the lower electrode side generally tends to be longer than that onthe upper electrode side. As a result, the difference between theirimpedances occurs, thereby posing another problem of further adding toasymmetry in its characteristics.

When comparison is made between the first and second via-holes 28 d and28 e in the conventional capacitance element, the depth of the secondvia-hole 28 e on the lower electrode side is deeper than the depth ofthe first via-hole 28 d on the upper side electrode side. This furtherincreases the conventional asymmetry of its characteristics.

SUMMARY OF THE INVENTION

The present invention was made in view of the foregoing points at issue.An object of the present invention is to provide a semiconductor deviceand its fabricating method capable of preventing the fluctuation incharacteristics such as capacitance value or deterioration ofreliability by damage caused to the upper electrode or dielectric filmduring the process of fabricating a capacitance element, and furthersuppressing an increase of asymmetry in characteristics, therebyallowing a capacitance element with satisfactory characteristics andhigh reliability to be implemented.

A semiconductor device according to the present invention comprises: alower electrode that is formed on a semiconductor substrate through afirst insulation film and has a recess form section in which the surfaceof its periphery lies on a higher level than that of its center; anupper electrode that is formed on the center of the lower electrodethrough a dielectric film the surface of which lies on a lower levelthan that of the periphery of lower electrode; and a second insulationfilm which fills a recess of the lower electrode having a recess formsection.

It should be noted that “the surface lies on a higher level” or “thesurface lies on a lower level” used herein is wording to express a levelof surface's height with respect to a flat plane of the top or bottomsurface of a semiconductor substrate. This definition is hereinafterapplied as well.

The present invention further comprises, in the above semiconductordevice, an inter-layer insulation film that is formed as a thirdinsulation film in the periphery of lower electrode, the upper electrodeand the second insulation film, a first wiring layer that is connectedto the upper electrode through a first via-hole opened in theinter-layer insulation film, and a second wiring layer that is connectedto the periphery of the lower electrode through a second via-hole openedin the inter-layer insulation film.

A semiconductor device according to the present invention comprises: alower electrode formed on a semiconductor substrate through a firstinsulation film; a dummy electrode formed around the lower electrode andhaving the surface higher than that of the lower electrode; an upperelectrode that is formed on the lower electrode through a dielectricfilm the surface of which lies on a lower level than the top surface ofthe dummy electrode; and a second insulation layer that fills a recesssurrounded by the dummy electrode.

It should be noted that “a dummy electrode having the surface higherthan that of the dielectric film” as described above means that the topsurface of the dummy electrode is higher than the surface of the lowerelectrode with a flat plane of the top or bottom surface of asemiconductor substrate as a reference. A description “the top surfaceof the dummy electrode” means the uppermost surface of surfaces of thedummy electrode. This definition is hereinafter applied as well.

The present invention further comprises, in the above semiconductordevice, an inter-layer insulation film that is formed as a thirdinsulation film on the dummy electrode, the upper electrode and thesecond insulation film, a first wiring layer that is connected to theupper electrode through a first via-hole opened in the inter-layerinsulation film, and a second wiring layer that is connected to theperiphery of the lower electrode through a second via-hole opened in theinter-layer insulation film.

A semiconductor device according to the present invention comprises: alower electrode that is formed on a semiconductor substrate through afirst insulation film and has a recess form section in which the surfaceof its periphery lies on a higher level than that of its center; anupper electrode that is formed on the center of the lower electrodethrough a dielectric film the surface of which lies on a lower levelthan that of the periphery of lower electrode; and a second insulationfilm which fills a recess of the lower electrode having a recess formsection and at the same time, covers the surface of the upper electrode.

The present invention further comprises, in the above semiconductordevice, an inter-layer insulation film that is formed as a thirdinsulation film in the periphery of lower electrode, the upper electrodeand the second insulation film, a first wiring layer that is connectedto the upper electrode through a first via-hole opened in theinter-layer insulation film, and a second wiring layer that is connectedto the periphery of the lower electrode through a second via-hole openedin the inter-layer insulation film.

A semiconductor device according to the present invention comprises: alower electrode formed on a semiconductor substrate through a firstinsulation film; a dummy electrode formed around the lower electrode andhaving the surface higher than that of the lower electrode; an upperelectrode formed on the lower electrode through the dielectric film andthe surface of which lies on a lower level than the top surface of thedummy electrode; and a second insulation layer that fills a recesssurrounded by the dummy electrode and at the same time, covers thesurfaces of the lower and upper electrodes.

It should be noted that “a dummy electrode having the surface higherthan that of the lower electrode” as described above means that the topsurface of the dummy electrode is higher than the surface of the lowerelectrode with a flat plane of the top or bottom surface of asemiconductor substrate as a reference. A description “the top surfaceof the dummy electrode” means the uppermost surface of surfaces of thedummy electrode. This definition is hereinafter applied as well.

The present invention further comprises, in the above semiconductordevice, an inter-layer insulation film that is formed as a thirdinsulation film on the dummy electrode, the upper electrode and thesecond insulation film, a first wiring layer that is connected to theupper electrode through a first via-hole opened in the inter-layerinsulation film, and a second wiring layer that is connected to theperiphery of the lower electrode through a second via-hole opened in theinter-layer insulation film.

In the aforementioned semiconductor device, a dummy layer for making alevel difference is provided below the periphery of the lower electrode,whereby the lower electrode is formed so as to have a recess formsection.

Also, in the above semiconductor device, a dummy layer for making alevel difference is provided below the dummy electrode, whereby thedummy electrode is formed so as to lie on a level higher than the lowerelectrode.

Such a dummy layer for making a level difference can be formed of thesame material as that of an electrode or a resistance layer of otherelement in a semiconductor device. The dummy layer for making a leveldifference can also be formed of an insulation layer.

According to a semiconductor device of the present invention, because itcomprises a lower electrode having a recess form section in which thesurface of its periphery lies on a higher level than the surface of itscenter, and an upper electrode formed on the center of the lowerelectrode through a dielectric film the surface of which lies on a lowerlevel than that of the periphery of lower electrode, namely, because thesurface of dielectric film on the center of lower electrode with arecess form section is lower than that of the periphery of lowerelectrode, when the second insulation film serving as a smoothinginsulation film on the whole surface of base body is formed, even if thesmoothing process of etching back an insulation film or the like piledon the whole surface of base body is executed, the periphery of lowerelectrode forms an etching stopper which can prevent the dielectric filmfrom sustaining damage. Therefore, it is possible to obtain acapacitance element having less fluctuation in its characteristics andhigh reliability.

Moreover, in a semiconductor device according to the present invention,the third insulation film is formed on the periphery of lower electrode,the upper electrode and the second insulation film to make aninter-layer insulation film; the first wiring layer connected to theupper electrode through the first via-hole opened in the inter-layerinsulation film on the upper electrode being formed; and the secondwiring layer connected to the periphery of lower electrode through thesecond via-hole opened in the inter-layer insulation film on theperiphery of lower electrode being formed. Thus, the film thickness ofinter-layer insulation film on the upper electrode to be etched foropening the first via-hole is approximately equal to that of inter-layerinsulation film on the periphery of lower electrode to be etched foropening the second via-hole. Therefore, when the first and secondvia-holes are opened, it is possible to prevent the dielectric filmunder the upper electrode from suffering damage due to an excessoveretching to the surface of upper electrode. Consequently, it ispossible to obtain a capacitance element which, in addition to the aboveadvantage, has still less fluctuation in its characteristics and higherreliability. Furthermore, in comparing the first via-hole with secondvia-hole, the depth of the second via-hole opened on the periphery oflower electrode is approximately equal to the depth of the firstvia-hole opened on the upper electrode. Thus, of the distances from anarea where the upper and lower electrodes are opposed to each other andwhich effectively functions as a capacitance element to the first andsecond wiring layers, the distance on the lower electrode side whichgenerally tends to be longer than that on the upper electrode side canbe shortened. Therefore, it is possible to reduce the difference oftheir impedances to suppress an increase of asymmetrical characteristicsof a capacitance element and thus improve symmetry of characteristicsthereof.

A semiconductor device according to the present invention comprises alower electrode, a dummy electrode formed around the lower electrode andhaving the surface higher than that of the lower electrode, and an upperelectrode formed on the lower electrode through a dielectric film,wherein the surface of the dielectric film on the lower electrode islower than the top surface of the dummy electrode around the lowerelectrode. Thus, when the second insulation film serving as a smoothinginsulation film is formed on the whole surface of base body, even if asmoothing process to etch back the insulation film piled on the wholesurface of base body is performed the dummy electrode becomes an etchingstopper and the dielectric film can be prevented from sustaining damage.Therefore, it is possible to obtain a capacitance element having lessfluctuation in its characteristics and high reliability.

A semiconductor device according to the present invention comprises alower electrode having a recess form section in which the surface of itsperiphery is on a higher level than that of its center, and an upperelectrode formed on the center of the lower electrode through adielectric film and having the surface lower than that of the peripheryof lower electrode. In other words, the surface of upper electrode onthe center of lower electrode having a recess form section is lower thanthat of the periphery of lower electrode. Thus, when the secondinsulation film serving as a smoothing insulation film is formed on thewhole surface of base body, the surface of the upper electrode is alwaysin a state covered by the second insulation film. As a result, even if asmoothing process to etch back the insulation film piled on the wholesurface of base body is executed, together with the fact that theperiphery of lower electrode acts as a etching stopper, it is possibleto prevent the upper electrode and further the dielectric filmthereunder from suffering damage. Therefore, it is possible to obtain acapacitance element having less fluctuation in its characteristics andhigh reliability.

Moreover, a semiconductor device according to the present inventionfurther comprises an inter-layer insulation film formed as a thirdinsulation film on a second insulation film covering the periphery oflower electrode and the surface of upper electrode, a first wiring layerconnected to the upper electrode through a first via-hole opened in theinter-layer insulation film on the upper electrode, and a second wiringlayer connected to the periphery of lower electrode through a secondvia-hole opened in the inter-layer insulation film on the periphery oflower electrode. Thus, the film thickness of inter-layer insulation filmon the upper electrode to be etched for opening a first via-hole isthicker than that of inter-layer insulation film on the periphery oflower electrode to be etched for opening a second via-hole.Consequently, when the first and second via-holes are opened, it ispossible to prevent the upper electrode and further a dielectric filmthereunder from sustaining damage due to excess overetching to thesurface of upper electrode. Therefore, it is possible to obtain acapacitance element which, in addition to the above advantage, has stillless fluctuation in its characteristics and high reliability.

Furthermore, in comparing the first via-hole with second via-hole, thedepth of the second via-hole opened on the periphery of lower electrodeis shallower than that of the first via-hole opened on the upperelectrode. Thus, of distances from an area where the upper electrode andlower electrode are opposed to each other and which functionseffectively as a capacitance element to the first and second wiringlayers, the distance on the lower electrode side which generally tendsto be longer than that on the upper electrode side is shortened. Thismakes the difference in their impedances small to suppress an increaseof asymmetry in characteristics of a capacitance element, therebyallowing symmetry in characteristics of the capacitance element to beimproved.

A semiconductor device according to the present invention comprises alower electrode, a dummy electrode formed around the lower electrode andhaving the surface higher than that of the lower electrode, and an upperelectrode formed on the lower electrode through a dielectric film,wherein the surface of upper electrode on the lower electrode is lowerthan the top surface of the dummy electrode around the lower electrode.Thus, when the second insulation film serving as a smoothing insulationfilm is formed on the whole surface of a base body, the secondinsulation film makes it possible to cover the surface upper electrodeeasily. Therefore, even if a smoothing process to etch back theinsulation film piled on the whole surface of the base body is executed,it is possible to prevent the upper electrode and further the dielectricfilm thereunder from sustaining damage as a result of the surface ofupper electrode being etched, together with the fact that the dummyelectrode acts as a etching stopper. Consequently, it is possible toobtain a capacitance element having less fluctuation in itscharacteristics and high reliability.

In a case where, in the above semiconductor device according to thepresent invention, the dummy layer for making a level differenceprovided below the periphery of lower electrode is formed of the samematerial as those of electrodes or resistance layers of other elementsin the semiconductor device, simplification of its fabrication can berealized. Also, in the case where the dummy layer for making a leveldifference provided below the dummy electrodes is formed of the sameconductor layer as are wiring layers of other elements in thesemiconductor device, its fabrication can be simplified.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference in the peripheryof a predefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; piling a conductor film onthese first insulation film and dummy layer and then patterning theconductor film so as to form a lower electrode with a recess formsection in which the surface of its periphery lies on a higher levelthan the surface of its center, in the predefined area of forming acapacitance element; forming an upper electrode through a dielectricfilm the surface of which lies on a lower level than that of theperiphery of lower electrode; and forming a second insulation film onthe whole surface of a base body to fill a recess of the lower electrodehaving a recess form section.

A method of fabricating a semiconductor device according to the presentinvention further comprises the steps of: forming a third insulationfilm on the whole surface of a base body including the periphery of thelower electrode, the upper electrode and the second insulation film toform an inter-layer insulation film; opening a first via-hole in theinter-layer insulation film on the upper electrode and also forming asecond via-hole in the inter-layer insulation film on the periphery ofthe lower electrode; and forming a first wiring layer connected to theupper electrode through the first via-hole and also forming a secondwiring layer connected to the periphery of the lower electrode throughthe second via-hole.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference in the peripheryof a predefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; piling a conductor film onthese first insulation film and dummy layer and then patterning theconductor film so as to form a lower electrode in the predefined area offorming a capacitance element and forming a dummy electrode in theperiphery of the predefined area of forming the capacitance element ascovers the dummy layer and has a surface higher than the surface of thelower electrode; and forming an upper electrode on the lower electrodethrough the dielectric film the surface of which lies on a lower levelthan the top surface of the dummy electrode; and forming a secondinsulation film on the whole surface of a base body to a recess theperiphery of which is surrounded by the dummy electrode.

A method of fabricating a semiconductor device according to the presentinvention further comprises the steps of: forming a third insulationfilm on the whole surface of the base body including the dummyelectrode, the upper electrode and the second insulation film to form aninter-layer insulation film; opening a first via-hole in the inter-layerinsulation film on the upper electrode and also forming a secondvia-hole in the inter-layer insulation film in the lower electrode; andforming a first wiring layer connected to the upper electrode throughthe first via-hole and also forming a second wiring layer connected tothe lower electrode through the second via-hole.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference around apredefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; piling a conductor film onthese first insulation film and dummy layer and then patterning theconductor film so as to form a lower electrode with a recess sectionform the surface of which lies on a higher level than the surfacethereof in the predefined area of forming the capacitance element;forming an upper electrode, whose surface lies on a lower level than thesurface of the periphery of the lower electrode, on the central part ofthe lower electrode through a dielectric film; and forming a secondinsulation film on the whole surface of a base body to fill a recesssection form of the lower electrode to cover the surface of the upperelectrode.

A method of fabricating a semiconductor device according to the presentinvention further comprises the steps of: forming a third insulationfilm on the whole surface of the base body including the dummy electrodeand the second insulation film to form an inter-layer insulation film;opening a first via-hole in the inter-layer insulation film on the upperelectrode and also opening a second via-hole in the inter-layerinsulation film on the lower electrode; and forming a first wiring layerconnected to the upper electrode through the first via-hole and alsoforming a second wiring layer connected to the lower electrode throughthe second via-hole.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference in the peripheryof a predefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; piling a conductor film onthese first insulation film and dummy layer and then patterning theconductor film so as to form a lower electrode in the predefined area offorming a capacitance element and forming a dummy electrode in theperiphery of the predefined area of forming the capacitance element ascovers the dummy layer and has a surface higher than the surface of thelower electrode; and forming an upper electrode the surface of whichlies on a lower level than the top surface of the dummy electrode, onthe lower electrode through the dielectric film; and forming a secondinsulation film on the whole surface of a base body to fill a recess theperiphery of which is surrounded by the dummy electrode and also coverthe surfaces of the lower and upper electrodes.

A method of fabricating a semiconductor device according to the presentinvention further comprises the steps of: forming a third insulationfilm on the whole surface of the base body including the dummyelectrode, the upper electrode and the second insulation film to form aninter-layer insulation film; opening a first via-hole in the inter-layerinsulation film on the upper electrode and also forming a secondvia-hole in the inter-layer insulation film in the lower electrode; andforming a first wiring layer connected to the upper electrode throughthe first via-hole and also forming a second wiring layer connected tothe lower electrode through the second via-hole.

In the above described method of fabricating a semiconductor device, theprocess of forming the dummy layer for making a level difference can becombined with the process of forming electrodes or resistance layers ofother elements in the semiconductor device. The dummy layer for making alevel difference can be formed of an insulation layer.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference in the peripheryof a predefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; patterning a conductor filmpiled on the dummy layer to form a lower electrode with a recess formsection in which the surface of its periphery lies on a higher levelthan the surface of its center in a predefined area of forming acapacitance element; and forming an upper electrode on the center oflower electrode through a dielectric film the surface of which lies on alower level than the surface of periphery of lower electrode. Thus, whenthe second insulation film serving as a smoothing insulation film isformed, even if a smoothing process to etch back the insulation filmpiled on the whole surface of a base body is executed, the periphery oflower electrode acts as an etching stopper, thereby allowing thedielectric film to be prevented from suffering damage. Therefore, it ispossible to obtain a capacitance element having less fluctuation in itscharacteristics and high reliability.

Moreover, a method of fabricating a semiconductor device according tothe present invention further comprises the steps of: forming a thirdinsulation film on the whole surface of the base body including theperiphery of the lower electrode, the upper electrode and the secondinsulation film to form an inter-layer insulation film; and then forminga first wiring layer connected to the upper electrode through the firstvia-hole opened in the inter-layer insulation film on the upperelectrode and also forming a second wiring layer connected to theperiphery of lower electrode through the second via-hole opened in theinter-layer insulation film on the periphery of lower electrode. Thus,the film thickness of the inter-layer insulation film on the upperelectrode to be etched for opening the first via-hole becomesapproximately equal to the film thickness of the inter-layer insulationfilm on the periphery of lower electrode to be etched for opening thesecond via-hole. Therefore, when the first and second via-holes areopened, it is possible to prevent the dielectric film under the upperelectrode from sustaining damage due to an excess overetching to thesurface of the upper electrode. Consequently, it is possible to obtain acapacitance element having in addition to the above advantage, stillless fluctuation in its characteristics and higher reliability.

In comparing the first via-hole with the second via-hole, the depth ofthe second via-hole opened on the lower electrode becomes approximatelyequal to the depth of the first via-hole opened on the upper electrode.Thus, of distances from an area where the upper and lower electrodes areopposed to each other and which effectively functions as a capacitanceelement to the first and second wiring layers, the distance on the lowerelectrode side which generally tends to be longer than that on the upperelectrode side is shortened. This makes the difference in theirimpedances decrease to thereby suppress an increase of asymmetry incharacteristics of a capacitance element and improve symmetry incharacteristics of the capacitance element.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference in the peripheryof a predefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; patterning thereafter aconductor film piled on these first insulation film and dummy layer toform a lower electrode in a predefined area of forming a capacitanceelement and also form a dummy electrode that covers the dummy layer andhas the surface higher than that of the lower electrode around thepredefined area of forming a capacitance element; and forming an upperelectrode on the lower electrode through a dielectric film the surfaceof which lies on a lower level than the top surface of the dummyelectrode. Thus, when a second insulation film serving as a smoothinginsulation film is formed, even if a smoothing process to etch back aninsulation film piled up all over the base body is executed, the dummyelectrode acts as an etching stopper, whereby it is possible to preventthe dielectric film from sustaining damage. Therefore, it is possible toobtain a capacitance element having less fluctuation in itscharacteristics and high reliability.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference in the peripheryof a predefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; patterning a conductor filmpiled on these first insulation film and dummy layer to form a lowerelectrode with a recess form section in which the surface of itsperiphery lies on a higher level than the surface of its center; andforming an upper electrode the surface of which lies on a lower levelthan the surface of the periphery of lower electrode on the center oflower electrode through a dielectric film, whereby it is possible toeasily materialize covering the surface of upper electrode by a secondinsulation film formed on the whole surface of a base body. Thus, whenthe second insulation film serving as a smoothing insulation film isformed, even if a smoothing process to etch back the insulation filmpiled on the whole surface of the base body, the periphery of lowerelectrode becomes an etching stopper, thereby making it possible toavoid that the surface of upper electrode is etched to cause damage tothe upper electrode and further the dielectric film thereunder.Therefore, it is possible to obtain a capacitance element having lessfluctuation in its characteristics and high reliability.

Moreover, a method of fabricating a semiconductor device according tothe present invention further comprises the steps of: forming a thirdinsulation film on the whole surface of a base body including theperiphery of the lower electrode and the second insulation film coveringthe surface of the upper electrode to form an inter-layer insulationfilm; and thereafter forming a first wiring layer connected to the upperelectrode through a first via-hole opened in the inter-layer insulationfilm on the upper electrode and also forming a second wiring layerconnected to the periphery of lower electrode through a second via-holeopened in the inter-layer insulation film on the periphery of lowerelectrode. As a result, the film thickness of the inter-layer insulationfilm on the upper electrode to be etched for opening the first via-holebecomes thicker than that of the inter-layer insulation film on theperiphery of lower electrode to be etched for opening the secondvia-hole. Thus, when the first and second via-holes are opened, it ispossible to prevent the upper electrode and further the dielectric filmthereunder from suffering damage due to an excess overetching to thesurface of upper electrode. Therefore, it is possible to obtain acapacitance element having, in addition to the above advantage, stillless fluctuation in its characteristics and higher reliability.

Also, in comparing the first via-hole with the second via-hole, thedepth of the second via-hole opened on the lower electrode becomesshallower than that of the first via-hole opened on the upper electrode.Thus, of distances from an area where the upper and lower electrodes areopposed to each other and which functions effectively as a capacitanceelement to the first and second wiring layers, the distance on the lowerelectrode side which generally tends to be longer is made shorter.Therefore, it is possible to reduce the difference in their impedancesand suppress an increase of asymmetry in characteristics of acapacitance element, thereby allowing symmetry in characteristics of thecapacitance element to be improved.

A method of fabricating a semiconductor device according to the presentinvention comprises the steps of: forming a dummy layer with apredetermined thickness for making a level difference around apredetermined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; patterning thereafter aconductor film piled on these first insulation film and dummy layer toform a lower electrode in the predefined area of forming a capacitanceelement and also form a dummy electrode that covers the dummy layer andhas the surface higher than the surface of lower electrode around thepredefined area of forming a capacitance element; and forming an upperelectrode the surface of which lies on a lower level than the topsurface of the dummy electrode, on the lower electrode through adielectric film. As a result, it is possible to easily materializecovering the surface of upper electrode by a second insulation filmformed on the whole surface of a base body. Thus, when the secondinsulation film serving as a smoothing insulation film is formed, evenif a smoothing process to etch back the insulation film piled on thewhole surface of the base body is executed, the dummy electrode becomesan etching stopper and so it is possible to prevent the upper electrodeand further the dielectric film thereunder from sustaining damage.Therefore, it is possible to obtain a capacitance element having lessfluctuation in its characteristics and high reliability.

In the above method of fabricating a semiconductor device according tothe present invention, by combining the process of forming the dummylayer for making a level difference with a process of forming anelectrode or a resistance layer of another element in a semiconductordevice, it is possible to aim at simplifying its fabrication process.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic sectional diagram showing a capacitance elementaccording to a first embodiment of the present invention.

FIG. 2 is a schematic sectional process diagram (No.1) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 3 is a schematic sectional process diagram (No.2) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 4 is a schematic sectional process diagram (No.3) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 5 is a schematic sectional process diagram (No.4) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 6 is a schematic sectional process diagram (No.5) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 7 is a schematic sectional process diagram (No.6) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 8 is a schematic sectional process diagram (No.7) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 9 is a schematic sectional process diagram (No.8) for explainingthe method of fabricating the capacitance element shown in FIG. 1.

FIG. 10 is a schematic sectional diagram showing a capacitance elementaccording to a second embodiment of the present invention.

FIG. 11 is a schematic sectional process diagram (No.1) for explainingthe method of fabricating the capacitance element shown in FIG. 10.

FIG. 12 is a schematic sectional process diagram (No.2) for explainingthe method of fabricating the capacitance element shown in FIG. 10.

FIG. 13 is a schematic sectional diagram showing a capacitance elementaccording to a third embodiment of the present invention.

FIG. 14 is a schematic sectional process diagram (No.1) for explainingthe method of fabricating the capacitance element shown in FIG. 13.

FIG. 15 is a schematic sectional process diagram (No.2) for explainingthe method of fabricating the capacitance element shown in FIG. 13.

FIG. 16 is a schematic sectional process diagram (No.3) for explainingthe method of fabricating the capacitance element shown in FIG. 13.

FIG. 17 is a schematic sectional process diagram (No.4) for explainingthe method of fabricating the capacitance element shown in FIG. 13.

FIG. 18 is a schematic sectional process diagram (No.5) for explainingthe method of fabricating the capacitance element shown in FIG. 13.

FIG. 19 is a schematic sectional process diagram (No.6) for explainingthe method of fabricating the capacitance element shown in FIG. 13.

FIG. 20 is a schematic sectional diagram showing a capacitance elementaccording to a fourth embodiment of the present invention.

FIG. 21 is a schematic sectional process diagram (No.1) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 22 is a schematic sectional process diagram (No.2) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 23 is a schematic sectional process diagram (No.3) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 24 is a schematic sectional process diagram (No.4) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 25 is a schematic sectional process diagram (No.5) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 26 is a schematic sectional process diagram (No.6) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 27 is a schematic sectional process diagram (No.7) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 28 is a schematic sectional process diagram (No.8) for explainingthe method of fabricating the capacitance element shown in FIG. 20.

FIG. 29 is a schematic sectional diagram showing a capacitance elementaccording to a fifth embodiment of the present invention.

FIG. 30 is a schematic sectional process diagram (No.1) for explainingthe method of fabricating the capacitance element shown in FIG. 29.

FIG. 31 is a schematic sectional process diagram (No.2) for explainingthe method of fabricating the capacitance element shown in FIG. 29.

FIG. 32 is a schematic sectional diagram showing a capacitance elementaccording to a sixth embodiment of the present invention.

FIG. 33 is a schematic sectional process diagram (No.1) for explainingthe method of fabricating the capacitance element shown in FIG. 32.

FIG. 34 is a schematic sectional process diagram (No.2) for explainingthe method of fabricating the capacitance element shown in FIG. 32.

FIG. 35 is a schematic sectional process diagram (No.3) for explainingthe method of fabricating the capacitance element shown in FIG. 32.

FIG. 36 is a schematic sectional process diagram (No.4) for explainingthe method of fabricating the capacitance element shown in FIG. 32.

FIG. 37 is a schematic sectional process diagram (No.5) for explainingthe method of fabricating the capacitance element shown in FIG. 32.

FIG. 38 is a schematic sectional process diagram (No.6) for explainingthe method of fabricating the capacitance element shown in FIG. 32.

FIG. 39 is a schematic sectional process diagram (No.1) for explaining aconventional method of fabricating a capacitance element.

FIG. 40 is a schematic sectional process diagram (No.2) for explainingthe conventional method of fabricating a capacitance element.

FIG. 41 is a schematic sectional process diagram (No.3) for explainingthe conventional method of fabricating a capacitance element.

DETAILED DESCRIPTION OF THE INVENTION

Modes for carrying out the invention, or embodiments of the presentinvention will be described below with reference to the accompanyingdrawings.

A First Embodiment

FIG. 1 is a schematic sectional diagram showing a capacitance elementaccording to a first embodiment of the present invention. FIG. 2 to FIG.9 are schematic sectional process diagrams for explaining the method offabricating the capacitance element shown in FIG. 1, respectively.

As shown in FIG. 1, in the capacitance element according to thisembodiment, there is formed a polysilicon dummy layer 14 for making alevel difference in the periphery of a predefined area of forming thecapacitance element on a semiconductor substrate 10 through a firstinsulation film 12 made of, e.g. a SiO₂ film. The dummy layer 14 is madeof a polysilicon layer having a predetermined thickness of, e.g. 100 nmto 500 nm or so. On the first insulation film 12 and the polysilicondummy layer 14 is formed a second insulation film 16. Note that thesecond insulation film 16 can be dispensed with.

Moreover, on the second insulation film 16 is formed a lower electrode18 a made of a TiN/Al—Si/Ti/TiON/Ti lamination film or Cu, Al—Cu and thelike. In the lamination film, for example a Ti layer with about 5 to 70nm thickness, a TiON layer with about 10 to 200 nm thickness, a Ti layerwith about 5 to 70 nm thickness, an Al—Si layer with about 300 to 1500nm thickness, and an TiN layer with about 5 to 70 nm thickness are piledin turn from below.

Specifically, the lower electrode 18 a has a recess form section inwhich the surface of its periphery on the polysilicon dummy layer 14with about 100 to 500 nm thickness for making a level difference lies ona higher level than the surface of its center by 100 to 500 nm or so.

Additionally, in the lower electrode 18 a of such a TiN/Al—Si/Ti/TiON/Timultilayer, the uppermost TiN layer functions as an antireflectioncoating in the photolithographing step during its fabrication processand as an antioxidation film of the Al—Si layer thereunder. The Al—Silayer functions as the principal part of electrodes that require aconductive characteristic. The lower Ti/TiON/Ti layered film functionsas a barrier metal.

Furthermore, on the center of the lower electrode 18 a is formed anupper electrode 22 made of Ti, TiN or a Ti/TiN layered film having 5 to100 nm or so thickness, through a dielectric film 20 made of Ta₂O₅, SiO₂or SiN and the like, having a predetermined thickness of, e.g. 10 to 300nm or so, in this embodiment Ta₂O₅ dielectric film. When the dielectricfilm 20 is formed of ta₂O₅, it is preferable to form the upper electrode22 out of TiN or a layered film in which TiN and Ti are piled in thisorder, TiN and the layered film being hard to react with oxygen. Whenthe dielectric film 20 is formed of SiO₂, SiN and the like, the upperelectrode 22 can be formed of Ti, TiN or a TiN/Ti layered film.

In this manner, a capacitance element is formed from the upper electrode22 and the lower electrode 18 a which sandwich the dielectric film 20between them.

Then, the surface of the upper electrode 22 formed on the center of thelower electrode 18 a with a recess form section of this capacitanceelement becomes lower than the surface of the periphery of lowerelectrode 18 a with a recess form section over the polysilicon dummylayer 14.

Moreover, a smoothing process to unevenness of a base body including theupper electrode 22 and lower electrode 18 a is performed. Specifically,a smoothing insulation film 24 comprised of SiO₂ film piled on the wholesurface of the base body, for example, using the plasma CVD method withthe TEOS as a raw material as well as SOG film coated thereon is formed.This smoothing insulation film 24 fills a recess of the lower electrode18 a with a recess form section and also covers the surface of upperelectrode 22.

Furthermore, on the smoothed whole surface of the base body, namely, onthe periphery of lower electrode 18 a and the smoothing insulation film24 is piled an insulation film 26 made of, e.g. SiO₂ film. The smoothinginsulation film 24 and insulation film 26 form an inter-layer insulationfilm 27.

Then, a first upper-layer wiring layer 30 a which is made of, e.g. anAl-alloy layer and connected to the upper electrode 22 is formed througha first via-hole 28 a opened in the inter-layer insulation film 27 onthe upper electrode 22.

Also, a second upper-layer wiring layer 30 b which is made of, e.g. anAl-alloy layer and connected to the periphery of lower electrode 18 a isformed through a second via-hole 28 b opened in the inter-layerinsulation film 27 on the periphery of lower electrode 18 a.

Next, a method of fabrication the capacitance element shown in FIG. 1will be described with reference to schematic sectional process diagramsof FIG. 2 to FIG. 9.

To begin with, as shown in FIG. 2, after the first insulation film 12which is made of, e.g. SiO₂ film is formed on the semiconductorsubstrate 10, for example, a polysilicon layer with a predeterminedthickness, e.g. about 100 to 500 nm thickness is further formed on thefirst insulation film 12. Subsequently, through the photolithographingprocess and RIE process, the polysilicon layer is selectively removed byetching to pattern it into a predetermined shape.

In this way, a polysilicon dummy layer 14 made of a polysilicon layer ofabout 100 to 500 nm thickness for making a level difference is formed onthe periphery of a predefined area of forming a capacitance element onthe semiconductor substrate 10 through the first insulation film 12.

It is noted that the process of forming the polysilicon dummy layer 14can be combined with the process of forming a polysilicon layer used asa gate electrode of other elements, e.g. MOSTr (Metal OxideSemiconductor Transistor), a resistance layer of a resistance element,and an electrode of BipTr (bipolar transistor) in LSI.

Next, as shown in FIG. 3, the second insulation film 16 is formed on thewhole surface of a base body including the polysilicon dummy layer 14for making a level difference. Note that the second insulation film 16may be omitted to form.

Next, as shown in FIG. 4, using the sputtering method for example, aconductor film with a predetermined thickness is formed. For example,the conductor film is a TiN/Al—Si/Ti/TiON/Ti lamination film 18comprised of a Ti layer with about 5 to 70 nm thickness, a TiON layerwith about 10 to 200 nm thickness, a Ti layer with about 5 to 70 nmthickness, an Al—Si layer with about 300 to 1500 nm thickness, and a TiNlayer with about 5 to 70 nm thickness which are piled in turn frombelow.

Additionally, in such a multilayered structure, the uppermost TiN layerfunctions as an antireflection coating in the photolithographing stepduring the fabrication process and as an antioxidation film of the Al—Silayer lying thereunder. The lower Ti/TiON/Ti lamination film functionsas a barrier metal.

Also, in the TiN/Al—Si/Ti/TiON/Ti lamination film 18, the surface ofpolysilicon dummy layer 14 with about 100 to 500 nm thickness for makinga level difference is higher than the surface of an area surrounded bythe polysilicon dummy layer 14 by 100 to 500 nm or so.

Next, as shown in FIG. 5, a dielectric film made of Ta₂O₅, SiO₂, SiN andthe like, in this embodiment Ta₂O₅ dielectric film is piled on theTiN/Al—Si/Ti/TiON/Ti lamination film 18, using the CVD method forexample, up to a predetermined thickness of, e.g. 10 to 300 nm or so.Further using the sputtering method for example, a conductor layer madeof, e.g. a Ti layer, a TiN layer or a Ti/TiN layered film is piled onthe dielectric film up to a predetermined thickness of, e.g. 5 to 100 nmor so.

Subsequently, through the photographing process and RIE process, theselayered conductor layer and dielectric film are selectively removed byetching into a predetermined pattern.

In this manner, an upper electrode 22 made of a Ti layer, or a Ti/TiNlayered film having a thickness of about 5 to 100 nm is formed on theTiN/Al—Si/Ti/TiON/Ti lamination film 18 in the area surrounded by thepolysilicon dummy layer 14 through the dielectric film 20 having athickness of about 10 to 300 nm.

Note that the surface of the upper electrode 22 at this time is lower inheight than the surface of a portion of the lamination film 18 situatedover the polysilicon dummy layer 14.

Next as shown in FIG. 6, through the photolithographing process and RIEprocess, the TiN/Al—Si/Ti/TiON/Ti lamination film 18 is selectivelyremoved by etching into a predetermined pattern.

A lower electrode 18 a made of the TiN/Al—Si/Ti/TiON/Ti lamination filmis thus formed. It has a recess form section in which the surface of itsperiphery over the polysilicon dummy layer 14 for making a leveldifference lies on a higher level than the surface of its center wherethe upper electrode 22 is formed. In addition, at the same time withforming the lower electrode 18 a, a lower wiring layer (not shown) madeof a TiN/Al—Si/Ti/TiON/Ti lamination film of other elements in LSI isformed.

In this manner, a capacitance element is formed. It is comprised of theupper electrode 22 and lower electrode 18 a that sandwich the dielectricfilm 20 between them.

Additionally, the surface of upper electrode 22 of the capacitanceelement at this time is lower in height than the surface of theperiphery of lower electrode 18 a situated over the polysilicon dummylayer 14.

Next, as shown in FIG. 7, a smoothing process to smooth unevenness ofthe whole surface of the base body is executed. Specifically, using theplasma CVD method for example, taking the TEOS as a raw material, on thewhole surface of the base body including the upper electrode 22 andlower electrode 18 a is piled, for example, a SiO₂ film up to athickness of 300 to 1500 nm or so. In addition, the SiO₂ film is coatedwith a SOG film. Thereafter, these SOG film and SiO₂ film are etchedback.

A smoothing insulation film 24 is thus formed. It fills a recess of thelower electrode 18 a having a recess form section and also covers thesurface of upper electrode 22 to smooth the whole surface of base body.

It is noted that, in the process of smoothing the whole surface of basebody, namely, the process of forming the smoothing insulation film 24,the surface of upper electrode 22 formed on the center of lowerelectrode 18 a with a recess form section is lower in level than thesurface of the periphery of lower electrode 18 a with a recess formsection situated over the polysilicon dummy layer 14. Also, in a generalsmoothing etch-back, the etching rate of SiO₂ is not so different fromthose of Ti and TiN, so that in the etch-back after the SOG film and SiOfilm are formed, although the surface of the periphery of lowerelectrode 18 a is exposed, the surface of upper electrode 22 is alwayscovered with the smoothing insulation film 24 and thus never be exposedby the etching. In other words, the upper electrode 22 and thedielectric film 20 thereunder will never sustain damage.

Next, as shown in FIG. 8, using the plasma CVD method for example, onthe whole surface of base body including the periphery of lowerelectrode 18 a and the smoothing insulation film 24 is piled aninsulation film 26 made of, e.g. SiO₂ film. The smoothing insulationfilm 24 and insulation film 27 form an inter-layer insulation film 27.

Subsequently, using the photolithographing process and dry etchingmethod, the inter-layer insulation film 27 on the upper electrode 22 isselectively removed by etching and also the inter-layer insulation film27 on the periphery of lower electrode 18 a is selectively removed byetching to open a first via-hole 28 a and a second via-hole 28 b,respectively. On this occasion, in order to decrease the contactresistance, only TiN layer on the surface of lower electrode 18 a maysometimes be removed.

It is noted at this time that a total film thickness of the inter-layerinsulation film 27 on upper electrode 22 to be etched for opening thefirst via-hole 28 a is thicker than a film thickness of the inter-layerinsulation film 26 on the periphery of lower electrode 18 a to be etchedfor opening the second via-hole 28 b. For this reason, when these firstand second via-holes 28 a and 28 b are opened, an excess overetching tothe surface of upper electrode 22 will never happen.

Next, as shown in FIG. 9, after an Al-alloy layer is piled using thesputtering method for example, the Al-alloy layer is processed using thephotolithographing process and dry etching method to form a firstupper-layer wiring layer 30 a and a second upper-layer wiring layer 30 bwhich are made of the Al-alloy layer and connect respectively to theupper electrode 22 and the periphery of lower electrode 18 a through thefirst and second via-holes 28 a and 28 b.

Simultaneously with the formation of the first and second upper-layerwiring layers 30 a and 30 b, upper-layer wiring layers (not shown) ofother elements in LSI are formed.

As described above, in this embodiment, the polysilicon dummy layer 14for making a level difference, which is made of a polysilicon layerhaving a thickness of about 100 to 500 nm is formed on the periphery ofa predefined area of forming the capacitance element on thesemiconductor substrate 10; the second insulation film 16 being formedon the whole surface of base body including the polysilicon dummy layer14; the lower electrode 18 a having a recess form section in which thesurface of its periphery situated over the polysilicon dummy layer 14lies on a higher level than the surface of its center being formed onthe second insulation film 16; the upper electrode 22 having apredetermined thickness of, e.g. about 10 to 300 nm, and the surface ofupper electrode 22 being made lower than the surface of the periphery oflower electrode 18 a situated over the polysilicon dummy layer 14. Thus,when the smoothing process in which SiO₂ film is piled on the wholesurface of the base body, further coated with SOG film and then they areetched back, the smoothing insulation film 24 which fills the recess oflower electrode 18 a with a recess form section to smooth the wholesurface of base body covers the surface of upper electrode 22 at alltimes. Therefore, the upper electrode 22 and further the dielectric film20 thereunder will never sustain damage due to the etching in thesmoothing process. Consequently, it is possible to suppress thefluctuation in characteristics such as a capacitance value or the likeof a capacitance element and the deterioration of reliability thereof,thus allowing a capacitance element having satisfactory characteristicsand high reliability to be obtained.

Moreover, when the first and second via-holes 28 a and 28 b arerespectively opened in order to form the first and second upper-layerwiring layers 30 a and 30 b connecting to the respective upper electrode22 and lower electrode 18 a of a capacitance element, a total filmthickness of the inter-layer insulation film 27 on upper electrode 22 tobe etched for opening the first via-hole 28 a is thicker than a filmthickness of the inter-layer insulation layer 26 on the periphery oflower electrode 18 a to be etched for opening the second via-hole 28 b.Thus, an excess overetching to the surface of upper electrode 22 willnever take place and so the upper electrode 22 and Ta₂O₂ dielectric film20 lying thereunder will never suffer damage. Therefore, it is possibleto further suppress the fluctuation in characteristics such as acapacitance element or the like and the deterioration of reliabilitythereof, thus enabling capacitance element having better characteristicsand higher reliability to be obtained.

Furthermore, in comparison between the first and second via-holes 28 aand 28 b, the depth of the second via-hole 28 b opened on the lowerelectrode 18 a is shallower than that of the first via-hole 28 a on theupper electrode 22. Thus, of distances from an area where the upperelectrode 22 and lower electrode 18 a are opposed and which functionseffectively as a capacitance element to the first and second upper-layerwiring layers 30 a and 30 b, the distance on the lower electrode sidewhich generally tends to be longer than that on the upper electrode sideis made shorter. Therefore, it is possible to reduce a difference intheir impedances to suppress an increase of asymmetry in characteristicsof a capacitance element, namely, improve a symmetry in characteristicsthereof.

A Second Embodiment

FIG. 10 is a schematic sectional diagram showing a capacitance elementaccording to a second embodiment of the present invention. FIG. 11 andFIG. 12 are schematic sectional process diagrams for explaining a methodof fabricating the capacitance element shown in FIG. 10, respectively.It is noted herein that the same elements as constituent elements of thecapacitance element of the first embodiment shown in FIG. 1 to FIG. 9are denoted by the same reference numerals and the description thereofis omitted.

As shown in FIG. 10, the capacitance element according to thisembodiment is characterized by comprising a dummy layer 32 for making alevel difference, which is an insulation dummy layer made of SiN, SiO₂or the like having a predetermined thickness, for example, made of a SiNlayer having a thickness of 100 to 500 nm or so, instead of thepolysilicon dummy layer 14 for making a level difference in thecapacitance element according to the first embodiment shown in FIG. 1.The other constituent elements are the same as in the case of the firstembodiment.

Next, a method of fabricating the capacitance element shown in FIG. 10will be described with reference to schematic sectional process diagramsof FIGS. 11 and 12.

To start with, as shown in FIG. 11, after the first insulation film 12made of, e.g. a SiO₂ film is formed on the semiconductor substrate 10,on the first insulation film 12 is further formed an insulation film ofa different kind from the first insulation film 12, e.g. a SiN filmhaving a thickness of 100 to 500 nm or so. Subsequently, by thephotolithographing process and etching process, the SiN film isselectively removed by etching into a predetermined pattern.

In this manner, a SiN dummy layer 32 made of a SiN film having athickness of 100 to 500 nm or so is formed on the periphery of apredefined area of forming a capacitance element on the semiconductorsubstrate 10 through the first insulation film 12.

Next, as shown in FIG. 12, the second insulation film 16 is formed onthe whole surface of the base body including the SiN dummy layer 32 inthe same way as processes of the first embodiment shown in FIG. 3 toFIG. 9. On the second insulation film 16 is formed aTiN/Al—Si/Ti/TiON/Ti lamination film 18 on which an upper electrode 22is formed through the dielectric film 20. By the photolithographingprocess and RIE process, the TiN/Al—Si/Ti/TiON/Ti lamination film 18 ispatterned to form the lower electrode 18 a having a recess form sectionin which the surface of its periphery situated over the SiN dummy layer32 lies on a higher level than the surface of its center where the upperelectrode 22 is formed.

In this way, the capacitance element comprised of the upper electrode 22and lower electrode 18 a that sandwich the dielectric film 20 betweenthem is formed.

Note that the surface of the upper electrode 22 of the capacitanceelement at this time is lower in level than the surface of the peripheryof lower electrode 18 a situated over the SiN dummy layer 32.

Subsequently, SiO₂ film is piled on the whole surface of base bodyincluding the upper electrode 22 and lower electrode 18 a and furthercoated with SOG film. Thereafter, the smoothing process to etch backthese SOG film and SiO₂ film is executed to fill the recess of lowerelectrode 18 a having a recess form section and also cover the surfaceof upper electrode 22 for forming the smoothing insulation film 24 thatsmooths the whole surface of base body.

It is noted that, in the smoothing process of the whole surface of basebody, i.e. the forming process of the smoothing insulation film 24, thesurface of upper electrode 22 formed on the center of lower electrode 18a with a recess form section is lower in level than the surface of theperiphery of lower electrode 18 a with a recess form section situatedover the SiN dummy layer 32. Under a general smoothing etch-backcondition an etch rate difference between SiO₂ and Ti or TiN is notgreat. Thus, when the SOG film and SiO₂ film are etched back, althoughthe surface of the periphery of lower electrode 18 a is exposed, thesurface of upper electrode 22 is always covered with the smoothinginsulation film 24 and will never be exposed by etching.

Subsequently, on the whole surface of base body including the peripheryof lower electrode 18 a and the smoothing insulation film 24 is piledthe insulation film 26 made of, e.g. SiO₂ film to form the inter-layerinsulation film 27 comprises of the smoothing insulation film 24 and theinsulation film 26. Then, the inter-layer insulation on film 27 on upperelectrode 22 is selectively removed etching and also the inter-layerinsulation film 27 on the periphery of lower electrode 18 a isselectively removed by etching for opening the first and secondvia-holes 28 a and 28 b. The TiN layer of the surface of lower electrode18 a may sometimes be removed.

It is noted that a total film thickness at this time of the inter-layerinsulation film 27 on upper electrode 22 to be etched for opening thefirst via-hole 28 a is thicker than a film thickness of the inter-layerinsulation film 26 on the periphery of lower electrode 18 a to be etchedfor opening the second via-hole 28 b. For this reason, when these firstand second via-holes 28 a and 28 b are opened, the surface of upperelectrode 22 will never be subjected to an excess overetching.

Subsequently, the first and second upper-layer wiring layers 30 a and 30b are formed, which are respectively connected to the upper electrode 22and the periphery of lower electrode through the first and secondvia-holes 28 a and 28 b.

As described above, in this embodiment, the SiN dummy layer 32 having apredetermined thickness of e.g. 100 to 500 nm or so for making a leveldifference is formed on the periphery of a predefined area of formingthe capacitance element on the semiconductor substrate 10 through thefirst insulation film 12; the second insulation film 16 being formed onthe whole surface of base body including the SiN dummy layer 32; thelower electrode 18 a having a recess form section in which the surfaceof its periphery situated over the SiN dummy layer 32 lies on a higherlevel than the surface of its center being formed on the secondinsulation film 16; and the upper electrode 22 being formed on thecenter through the dielectric film 20 so that the surface of upperelectrode 22 being formed on the center through the dielectric film 20so that the surface of upper electrode 22 may be lower in level than thesurface of periphery of lower electrode 18 a situated over the SiN dummylayer 32. Thus, when the smoothing process is executed, which etchesback after SiO₂ film is piled on the whole surface of base body andfurther coated with SOG film, the smoothing insulation film 24 whichsmooths the whole surface of base body by filling the recess of lowerelectrode 18 a having a recess form section covers the surface of upperelectrode 22 at all times. Therefore, the upper electrode 22 and furtherthe dielectric film 20 thereunder will never sustain damage due to theetching in smoothing process. In consequence, similarly to the case ofthe first embodiment, it is possible to suppress the fluctuation incharacteristics such as a capacitance value or the like and thedeterioration of reliability on a capacitance element, thus allowing acapacitance element with satisfactory characteristics and highreliability to be obtained.

Moreover, when the first and second via-holes 28 a and 28 b are openedso as to form the first and second upper-layer wiring layers 30 a and 30b connected respectively to the upper electrode 22 and lower electrode18 a of the capacitance element, a total film thickness of theinter-layer insulation film 27 on the upper electrode 22 to be etchedfor opening the first via-hole 28 a is thicker than a film thickness ofthe inter-layer insulation film on the periphery of lower electrode 18 ato be etched for opening the second via-hole 28 b. This means that anexcess overetching to the surface of upper electrode 22 will neverhappen and so the upper electrode 22 and further the dielectric film 20thereunder will never suffer damage. Therefore, just like the case ofthe first embodiment, it is possible to further suppress the fluctuationin characteristics such as a capacitance value or the like and thedeterioration of reliability on a capacitance element, thus allowing acapacitance element with better characteristics and a higher reliabilityto be obtained.

Furthermore, the depth of the second via-hole 28 b opened on the lowerelectrode 18 a is shallower than the depth of the first via-hole 28 aopened on the upper electrode 22. Due to this fact, of distances from anarea where the upper electrode 22 and lower electrode 18 a are opposedand which effectively functions as a capacitance element to the firstand second upper-layer wiring layers 30 a and 30 b, a distance on thelower electrode side which generally tends to be longer than that on theupper electrode side is made shorter. For this reason, similarly to thecase of the first embodiment, it is possible to suppress an increase ofasymmetry in characteristics of a capacitance element by reducing thedifference in their impedances and so improve symmetry incharacteristics of the capacitance element.

Additionally, in the second embodiment, a SiN dummy layer 32 having apredetermined thickness of, e.g. 100 to 500 nm or so for making a leveldifference is formed on the periphery of a predefined area of forming acapacitance element on the semiconductor substrate 10 through the firstinsulation film 12. However, instead of forming such a SiN dummy layer32, the first insulation film 12 in the center of the predefined area offorming a capacitance element on the semiconductor substrate 10 mayselectively be removed by etching through the photolithographing processand etching process to form a recess having a depth of 100 to 500 nm orso. In addition, the selective etching of the first insulation film 12may be combined with forming the dummy layer 32(or the dummy layer 14, adummy layer 34 described below) so as to form a final dummy layer andthus form the recess having a depth of 100 to 500 nm or so.

In any of these cases, similarly to the case of the above secondembodiment, it is possible to form the second insulation film 16 on thefirst insulation film 12 in which the recess with a depth of 100 to 500nm or so is formed in the center of the predefined area of forming thecapacitance element; form a TiN/Al—Si/Ti/TiON/Ti lamination film 18 onthe second insulation from 16; pattern this TiN/Al—Si/Ti/TiON/Tilamination film 18; and thereby form the lower electrode 18 a having arecess form section in which the surface of its periphery lies on ahigher level than the surface of its center situated above the recessformed on the first insulation film 12. Therefore, the same function andresult as the case of the second embodiment can be effected.

A Third Embodiment

FIG. 13 is a schematic sectional diagram showing a capacitance elementaccording to a third embodiment of the present invention. FIG. 14 toFIG. 19 are schematic sectional process diagrams for explaining a methodof fabricating the capacitance element shown in FIG. 13, respectively.It is noted herein that the same elements as constituent element of thecapacitance element shown in FIG. 1 to FIG. 9 of the first embodimentare denoted by the same reference numerals to omit the descriptionthereof.

As shown in FIG. 13, in comparison with the capacitance element of thefirst embodiment shown in FIG. 1, a capacitance element according tothis embodiment is characterized in that, in stead of the polysilicondummy layer 14 for making a level difference being formed on theperiphery of a capacitance element, a polysilicon dummy layer 34 havingthe same thickness of, e.g. 100 to 500 nm or so for making a leveldifference is formed in the circumference of a capacitance element.

Moreover, it is also characterized in that, in stead of the lowerelectrode 18 a with a recess form section made of, e.g.TiN/Al—Si/Ti/TiON/Ti multilayer of the first embodiment shown in FIG. 1,a lower electrode 18 b having a flat surface and made of, e.g.TiN/Al—Si/Ti/TiON/Ti multilayer is formed. Separately from the lowerelectrode 18 b, a dummy electrode 18 c made of, e.g.TiN/Al—Si/Ti/TiON/Ti multilayer and having a higher surface than that ofupper electrode 22 is formed over the polysilicon dummy layer 34 formaking a level difference surrounding the capacitance element.

Thus, in contrast with the first embodiment in which the smoothinginsulation film 24 filling the recess of lower electrode 18 a with arecess form section covers the surface of upper electrode 22, thesmoothing insulation film 24 in this embodiment filling the recesssurrounded by the dummy electrode 18 c covers the surface of upperelectrode 22 formed above the lower electrode 18 b.

The other constituent elements are nearly the same as in the firstembodiment.

Next, a method of fabricating the capacitance element shown in FIG. 13will be described with reference to schematic sectional process diagramsof FIG. 14 to FIG. 19.

To start with, as shown in FIG. 14, after the first insulation film 12made of, e.g. a SiO₂ film is formed on the semiconductor substrate 10,on the first insulation film 12 is further formed, e.g. a polysiliconlayer having a predetermined thickness of, e.g. 100 to 500 nm or so.Subsequently, by the photolithographing process and RIE process, thepolysilicon layer is selectively removed by etching into a predeterminedpattern.

In this manner, the polysilicon dummy layer 34 made of a polysiliconlayer with a thickness of 100 to 500 nm or so is formed on the peripheryof the predefined area of forming the capacitance element on thesemiconductor substrate 10 through the first insulation film 12.

Note that the forming process of the polysilicon dummy layer 34 can becombined with the forming process of polysilicon layers used as a gateelectrode of other element, e.g. MOSTr, a resistance layer of aresistance element, and an electrode of BipTr in LSI.

Next, as shown in FIG. 15, in the same way as processes of the firstembodiment shown in FIG. 3 to FIG. 5, the second insulation film 16 isformed on the whole surface of the base body including the polysilicondummy layer 34 for making a level difference. The insulation film 16 maybe omitted to form. Then, on the second insulation film 16 is formedTiN/Al—Si/Ti/TiON/Ti lamination film or a layered film made of Cu, Al—Cuand the like, in this embodiment a TiN/Al—Si/Ti/TiON/Ti lamination film18. On the TiN/Al—Si/Ti/TiON/Ti lamination film 18 is formed the upperelectrode 22 made of a Ti layer, a TiN layer or a Ti/TiN layered filmthrough the dielectric film 20 made of Ta₂O₅, SiO₂, SiN and the like, inthis embodiment Ta₂O₅.

Additionally, the surface of upper electrode 22 at this time is lower inlevel than the top surface of the TiN/Al—Si/Ti/TiON/Ti lamination film18 situated over the polysilicon dummy layer 34.

Next, as shown in FIG. 16, through the photolithographing process andRIE process, the TiN/Al—Si/Ti/TiON/Ti lamination film 18 is selectivelyremoved by etching into a predetermined pattern.

In this way, the lower electrode 18 b made of a TiN/Al—Si/Ti/TiON/Tilamination film is formed in the predefined area of forming thecapacitance element on the second insulation film 16 and also,separately from the lower electrode 18 b, the dummy electrode 18 c madeof the TiN/Al—Si/Ti/TiON/Ti lamination film is formed over thepolysilicon dummy layer 34 surrounding the predefined area of formingthe capacitance element. The dummy layer 18 c has the top surface higherthan the surface of lower electrode 18 b.

Simultaneously with forming the lower electrode 18 b, a lower-layerwiring layer (not shown) made of the TiN/Al—Si/Ti/TiON/Ti laminationfilm of other element in LSI is formed.

The capacitance element comprised of the upper electrode 22 and lowerelectrode 18 b that sandwich the dielectric film 20 between them is thusformed.

Note that the surface of upper electrode 22 of capacitance element atthis time is lower in level than the top surface of dummy electrode 18 csurrounding the area forming the capacitance element and lying over thepolysilicon dummy layer 34.

Next, as shown in FIG. 17, a SiO₂ film having a thickness of 300 to 1500nm or so is piled on the whole surface of base body including the upperelectrode 22 and lower electrode 18 b and is further coated with a SOGfilm. Thereafter, the smoothing process to etch back these SOG film andSiO₂ film takes place.

In this manner, the smoothing insulation film 24 is formed, whichsmooths the whole surface of base body by filling the recess surroundedby dummy electrode 18 c and also covering the surface of upper electrode22 and lower electrode 18 b.

Additionally, in the process of smoothing the whole surface of basebody, i.e. the process of forming the smoothing insulation film 24, thesurface of upper electrode 22 formed on the lower electrode 18 b islower in level than the top surface of dummy electrode 18 c surroundingthe area of forming the capacitance element and lying over thepolysilicon dummy layer 34. For this reason, when the SOG film and SiO₂film are etched back, the surface of lower electrode 18 b and also thesurface of upper electrode 22 are always covered with the smoothinginsulation film 24 and will never be exposed by etching.

Next, as shown in FIG. 18, using the plasma CVD method for example, onthe whole surface of base body including the dummy electrode 18 c andsmoothing insulation film 24 is piled the inter-layer insulation film27.

Subsequently, using the photolithographing process and dry etchingmethod, the inter-layer insulation film 27 on the upper electrode 22 andlower electrode 18 b is selectively removed by etching to open the firstand second via-holes 28 a and 28 c.

Next, as shown in FIG. 19, after, e.g. Al-alloy layer is piled by thesputtering method for example, the Al-alloy layer is processed, usingthe photolithographing process and dry etching method, to form the firstand second upper-layer wiring layers 30 a and 30 c made of the Al-alloylayer and each connected to the upper electrode 22 and the periphery oflower electrode 18 b through the first and second via-holes 28 a and 28c.

Also, simultaneously with forming the first and second upper-layerwiring layers 30 a and 30 c, upper layer wiring layers (not shown) ofother elements in LSI are formed.

As described above, in this embodiment, the polysilicon dummy layer 34having a thickness of 100 to 500 nm or so for making a level differenceis formed on the periphery of the predefined area of forming thecapacitance element on the semiconductor substrate 10 through the firstinsulation film 12; the lamination film 18 made of, e.g. aTiN/Al—Si/Ti/TiON/Ti multilayer being formed on the whole surface ofbase body including the polysilicon dummy layer 34 through the secondinsulation film 16 to be patterned into a predetermined shape, therebyforming the lower electrode 18 b made of the TiN/Al—Si/Ti/TiON/Timultilayer in the predefined area of forming the capacitance element;and the dummy electrode 18 c made of the TiN/Al—Si/Ti/TiON/Ti multilayerhaving the surface higher than the surface of lower electrode 18 b beingformed over the polysilicon dummy layer 34 surrounding the lowerelectrode 18 b. At the same time, the upper electrode 22 is formed onthe lower electrode 18 b through the dielectric film 20 so that thesurface of upper electrode 22 may be lower in level than the top surfaceof dummy electrode 18 c situated over the polysilicon dummy layer 34.Thus, when SiO₂ film that is piled on the whole surface of base body andfurther coated with SOG film is etched back to perform the smoothingprocess the smoothing insulation film 24 which fills the recesssurrounded by the dummy electrode 18 c to smooth the whole surface ofbase body covers the surface of upper electrode 22 at all times. Forthis reason, the upper electrode 22 and further the dielectric film 20lying thereunder will never sustain damage due to etching in thesmoothing process. Therefore, similarly to the case of the firstembodiment, it is possible to suppress the fluctuation incharacteristics such as a capacitance value or the like and thedeterioration of reliability of a capacitance element, thus enabling acapacitance element having satisfactory characteristics and highreliability to be obtained.

Additionally, in the first to third embodiments described above, thecase where the lower electrode 18 a or 18 b is connected to the secondupper-layer wiring layer 30 b or 30 c through the second via-hole 28 bor 28 c is described. However, there are cases where the lower electrode18 a or 18 b also serve as a wiring layer and connect to other elementin LSI.

In this case, it is unnecessary that the inter-layer insulation film 27on the lower electrode 18 a or 18 b is selectively removed by etching toopen the second via-hole 28 b or 28 c.

Moreover, the first and second upper-layer wiring layers 30 a, 30 b or30 c may be formed in the following way. After a W (tungsten)-layer ispiled using the CVD method instead of piling and processing the Al-alloylayer, the W layer is etched back to form a W-plug which fills the firstand second via-holes 28 a, 28 b or 28 c. Further, an Al-alloy layer ispiled by the sputtering method and then the Al-alloy layer is processedusing the photolithographing process and dry etching method to form thefirst and second upper-layer wiring layers which connect to the W-pluginside the first and second via-holes 28 a, 28 b or 28 c.

A Fourth Embodiment

FIG. 20 is a schematic sectional diagram showing a capacitance elementaccording to a fourth embodiment of the present invention. FIG. 21 toFIG. 28 are schematic sectional process diagrams for explaining a methodof fabricating the capacitance element shown in FIG. 20.

As shown in FIG. 20, in the capacitance element according to thisembodiment, the polysilicon dummy layer 14 made of a polysilicon layerhaving a predetermined thickness of, e.g. 100 to 500 nm or so for makinga level difference is formed on the periphery of the predefined area offorming the capacitance element on the semiconductor substrate 10through the first insulation film 12 made of, e.g. a SiO₂ film. On thefirst insulation film 12 and the polysilicon dummy layer 14 is formedthe second insulation film 16. Additionally, the second insulation film16 can be dispensed with.

Further, on the second insulation film 16 is formed the lower electrode18 a made of the TiN/Al—Si/Ti/TiON/Ti lamination film or Cu, Al—Cu andthe like. The lamination film is such that a Ti layer having a thicknessof, e.g. about 5 to 70 nm, a TiON layer having a thickness of, e.g.about 10 to 200 nm, a Ti layer having a thickness of, e.g. about 300 to1500 nm, and a TiN layer having a thickness of, e.g. about 5 to 70 nmare piled in turn from below. In this embodiment, the lower electrode 18a of TiN/Al—Si/Ti/TiON/Ti lamination film is formed.

In other words, in the lower electrode 18 a having a recess formsection, the surface of its periphery situated over the polysilicondummy layer 14 having a thickness of, e.g. 100 to 500 nm or so formaking a level difference lies on a higher level than the surface of itscenter by 100 to 500 nm or so.

It is noted that, in the lower electrode 18 a having such aTin/Al—Si/Ti/TiON/Ti multilayer structure, the uppermost TiN layerfunctions as an antireflection coating in the photolithographing stepduring the fabrication process and as an antioxidation film of the Al—Silayer thereunder. The Al—Si layer functions as the principal part of theelectrode needing a conductive characteristic. The lower Ti/TiON/Tilamination film functions as a barrier metal.

Moreover, on the center of lower electrode 18 a is formed the upperelectrode 22 having a thickness of 5 to 100 nm or so, made of a Tilayer, a TiN layer or a Ti/TiN layered film, through the dielectric film20 having a predetermined thickness of, e.g. 10 to 300 nm or so and madeof Ta₂O₅, SiO₂, SiN or the like, in this embodiment Ta₂O₅ dielectricfilm. When the dielectric film 20 is made of Ta₂O₅, it is preferable toform the upper electrode 22 out of a TiN layer or a layered film inwhich TiN and Ti are piled in this order those being hard to react withoxygen. When the dielectric film 20 is made of SiO₂, SiN and the like,the upper electrode 22 can be formed out of a Ti layer, a TiN layer or aTiN/Ti layered film. In this way, the capacitance element is formed fromthe upper electrode 22 and lower electrode 18 a which sandwich thedielectric film 20 between them.

Then, the surface of dielectric film 20 formed on the center of lowerelectrode 18 a with a recess form section of the capacitance element islower in level than the surface of the periphery of lower electrode 18 awith a recess form section situated over the polysilicon dummy layer 14.

Furthermore, the smoothing process to smooth unevenness of the surfaceof base body including the upper electrode 22 and lower electrode 18 atakes place. Specifically, using the plasma CVD method for example,taking the TEOS as a raw material, the smoothing insulation film 24 madeof SiO₂ film piled on the whole surface of base body and SOG film coatedthereon is formed. The smoothing insulation film 24 fills the recess ofthe lower electrode 18 a having a recess form section.

Also, on the whole surface of the smoothed base body, namely, on theperiphery of lower electrode 18 a and the smoothing insulation film 24,the insulation film 26 made of, e.g. SiO₂ film is piled. The smoothinginsulation film 24 and the insulation film, 26 form the inter-layerinsulation film 27 together.

In addition, the first upper-layer wiring layer 30 a made of, e.g. anAl-alloy layer and connected to the upper electrode 22 is formed throughthe first via-hole 28 a opened in the inter-layer insulation film 27 onthe upper electrode 22.

Also, the second upper-layer wiring layer 30 b made of, e.g. an Al-alloylayer and connected to the periphery of lower electrode 18 a is formedthrough the second via-hole 28 b opened in the inter-layer insulationfilm 27 on the periphery of lower electrode 18 a.

Next, a method of fabricating the capacitance element shown in FIG. 20will be described with reference to schematic sectional process diagramsof FIG. 21 to FIG. 28.

Initially, as shown in FIG. 21, after the first insulation film 12 madeof, e.g. SiO₂ film is formed on the semiconductor substrate 10, furtheron the first insulation film 12 is formed, e.g. a polysilicon layerhaving a predetermined thickness of, e.g. 100 to 500 nm. Subsequently,by the photolithographing process and RIE process, the polysilicon layeris selectively removed by etching to pattern into a predetermined shape.

In this manner, the polysililcon dummy layer 14 made of a polysiliconlayer having a thickness of 100 to 500 nm or so is formed on theperiphery of the predefined area of forming the capacitance element onthe semiconductor substrate 10 though the first insulation film 12.

It is noted that the forming process of the polysilicon dummy layer 14can be combined with the forming process of a polysilicon layer used asa gate electrode of other element, e.g. MOSTr(metal oxide semiconductortransistor), a resistance layer of a resistance element, and anelectrode of BipTr (bipolar transistor) in LSI.

Next, as shown in FIG. 22, on the whole surface of base body includingthe polysilicon dummy layer 14 for making a level difference is formedthe second insulation film 16. Note that the second insulation film 16can be omitted to form.

Next, as shown in FIG. 23, using the sputtering method for example, onthe second insulation film 16 is formed a conductor film having apredetermined thickness, e.g. the TiN/Al—Si/Ti/TiON/Ti lamination film18 in which a Ti layer having a thickness of 5 to 70 nm or so, a TiONlayer having a thickness 10 to 200 nm or so, a Ti layer having athickness of 5 to 70 nm or so, a Al—Si layer having a thickness of 300to 1500 nm or so, and a TiN layer having a thickness of 5 to 70 nm or soare piled in turn from below.

Additionally, in such a multi-layered structure, the uppermost TiN layerfunctions as an antireflection coating in the photolithographing stepduring fabrication process and as an antioxidation film of the Al—Silayer thereunder. The Al—Si layer functions as the principal part of theelectrode requiring a conductive characteristic. The lower Ti/TiON/Tilamination film functions as a barrier metal.

Again, in the TiN/Al—Si/Ti/TiON/Ti lamination film 18, its surface overthe polysilicon dummy layer 14 with a thickness of 100 to 500 nm formaking a level difference is higher than the surface of an areasurrounded by the polysilicon dummy layer 14 by 100 to 500 nm or so.

Next, as shown in FIG. 24, using the CVD method for example, on theTiN/Al—Si/Ti/TiON/Ti lamination film 18 is piled the dielectric film 20made of Ta₂O₅, SiO₂, SiN or the like, in this embodiment Ta₂O₅dielectric film 20 having a predetermined thickness of, e.g. 10 to 300nm or so. Further, using the sputtering method for example, on thedielectric film is piled a conductor layer made of, e.g. a Ti layer, aTiN layer, or a Ti/TiN layered film having a predetermined thickness of,e.g. 20 to 500 nm or so.

Subsequently, via the photolithographing process and RIE process, theselayered conductor layer and dielectric film are selectively removed byetching into a predetermined pattern.

In this way, on the TiN/Al—Si/Ti/TiON/Ti lamination film 18 in an areasurrounded by the polysilicon dummy layer 14 for making a leveldifference, there is formed the upper electrode 22 made of a Ti layer, aTiN layer or a Ti/TiN layered film having a thickness of 20 to 500 nm orso through the dielectric film 20 having a thickness of 10 to 300 nm orso. The surface of upper electrode 22 is made equal to or higher than inlevel, the surface of lamination film 18 situated over the dummy layer14.

Note that the surface of dielectric film 20 at this time is lower inlevel than the surface of lamination film 18 situated over thepolysilicon dummy layer 14.

Next, as shown in FIG. 25, via the photolithographing process and RIEprocess, the TiN/Al—Si/Ti/TiON/Ti lamination film 18 is selectivelyremoved by etching into a predetermined pattern.

In this manner, the lower electrode 18 a made of theTiN/Al—Si/Ti/TiON/Ti lamination film having a recess form section inwhich the surface of its periphery over the polysilicon dummy layer 14for making a level difference lies on a higher level than the surface ofdielectric film 20 in its center having the upper electrode 22 formedthereon, is formed. Also, simultaneously with the formation of lowerelectrode 18 a, a lower layer wiring layer (not shown) made of aTiN/Al—Si/Ti/TiON/Ti lamination film of other element in LSI is formed.

The capacitance element comprised of the upper electrode 22 and lowerelectrode 18 a which sandwich the dielectric film 20 between them isthus formed.

Additionally, the surface of dielectric film 20 in the capacitanceelement at this time is lower in level than the surface of the peripheryof lower electrode 18 a located over the polysilicon dummy layer 14.

Next, as shown in FIG. 26, the smoothing process to smooth unevenness ofthe whole surface of base body is carried out. Specifically, using theplasma CVD method for example, taking the TEOS as a raw material, on thewhole surface of base body including the upper electrode 22 and lowerelectrode 18 a is piled, for example, a SiO₂ film up to a thickness of300 to 1500 nm or so. Further, the SiO₂ film is coated with a SOG film.Thereafter, these SOG film and SiO₂ film are etched back.

In this way, the smoothing insulation film 24 which fills the recess oflower electrode 18 a with a recess form section and smooths the wholesurface of base body is formed.

It is noted that, in the smoothing process of the whole surface of basebody, i.e. the formation process of the smoothing insulation film 24,the surface of dielectric film 20 formed on the center of lowerelectrode 18 a with a recess form section is lower in level than thesurface of the periphery of lower electrode 18 a with a recess formsection located over the polysilicon dummy layer 14. Moreover, in ageneral smoothing etch-back, an etching rate of SiO₂ is not so differentfrom that of Ti or TiN. Thus, when the SOG film and SiO₂ film are formedand then etched back, the surface of the periphery of lower electrode 18a is exposed, but the surface of dielectric film 20 will never beexposed by etching. In other words, the periphery of lower electrode 18a will serve as an etching stopper and so the dielectric film 20 underthe upper electrode 22 will never sustain damage.

Next, as shown in FIG. 27, using the plasma CVD method for example, onthe whole surface of base body including the periphery of lowerelectrode 18 a and the smoothing insulation film 24 is piled theinsulation film 26 made of, e.g. a SiO₂ film. The smoothing insulationfilm 24 and insulation film 26 form the inter-layer insulation film 27together.

Subsequently, using the photolithographing process and dry etchingmethod, the inter-layer insulation film 27 on upper electrode 22 isselectively removed by etching and also the inter-layer insulation film27 on the periphery of lower electrode 18 a is selectively removedetching for opening the first and second via-holes 28 a and 28 b. Atthis time, there may be a case where only the TiN layer on the surfaceof lower electrode 18 a is removed so as to reduce a contact resistance.

It is noted that, on this occasion, a film thickness of the inter-layerinsulation film 27 on upper electrode 22 to be etched for opening thefirst via-hole 28 a is approximately equal to a film thickness of theinter-layer insulation film 27 on the periphery of lower electrode 18 ato be etched for opening the second via-hole 28 b. For this reason, whenthese first and second via-holes 28 a and 28 b are opened, an excessover-etching to the surface of upper electrode 22 will never happen.

Next, as shown in FIG. 28, for example, an Al-alloy layer is piled usingthe sputtering method and then the Al-alloy layer is processed using thephotolithographing process and dry etching method in order to form thefirst and second upper-layer wiring layers 30 a and 30 b made of theAl-alloy layer connected to the upper electrode 22 and the periphery oflower electrode 18 a through the first and second via-holes 28 a and 28b.

Also, simultaneously with the formation of the first and secondupper-layer wiring layers 30 a and 30 b, upper-layer wiring layers (notshown) of other element is LSI is formed.

As described above, in this embodiment, the polysilicon dummy layer 14for making a level difference made of a polysilicon layer having athickness of 100 to 500 nm or so is formed on the periphery of apredefined area of forming the capacitance element on the semiconductorsubstrate 10 through the first insulation film 12; the second insulationfilm 16 being formed on the whole surface of base body including thepolysilicon dummy layer 14; the lower electrode 18 a with a recess formsection in which the surface of its periphery lies on a higher levelthan the surface of its center being formed on the insulation film 16;the upper electrode 22 having a predetermined thickness of, e.g. 5 to100 nm or so being formed on the center of lower electrode 18 a throughthe dielectric film 20 having a predetermined thickness of, e.g. 10 to300 nm (that is, a dielectric film thinner than the dummy layer 14); andthe surface of dielectric film 20 being made lower in level than thesurface of the periphery of lower electrode 18 a located over thepolysilicon dummy layer 14. Thus, after the SiO₂ film is piled on thewhole surface of base body and further coated with the SOG film, whenthe smoothing process to etch back them is carried out, the periphery oflower electrode 18 a acts as an etching stopper and so the dielectricfilm 20 will never suffer damage due to etching. Therefore, it ispossible to suppress the fluctuation in characteristics such as acapacitance value or the like and the deterioration of reliability on acapacitance element and thus obtain a capacitance element havingsatisfactory characteristics and a high reliability.

Moreover, when the first and second via-holes 28 a and 28 b are openedin order to form the first and second upper-layer wiring layers 30 a and30 b which are connected to the upper electrode 22 and lower electrode18 a, respectively, a film thickness of the inter-layer insulation film27 on the upper electrode 22 to be etched for opening the first via-hole28 a is approximately equal to a film thickness of the inter-layerinsulation film 27 on the periphery of lower electrode 18 a to be etchedfor opening the second via-hole 28 b. For this reason, an excessoveretching to the surface of upper electrode 22 will never be performedand so the upper electrode 22 and Ta₂O₅ dielectric film 20 thereunderwill never sustain damage. Therefore, it is possible to further suppressthe fluctuation in characteristics such as a capacitance value or thelike and the deterioration of reliability on a capacitance element andthus obtain a capacitance element having better characteristics andhigher reliability.

Furthermore, in comparison between the first and second via-holes 28 aand 28 b, the depth of the second via-hole 28 b opened on the lowerelectrode 18 a is shallower than the depth of the first via-hole 28 a.Thus, of distances from the area where the upper electrode 22 and lowerelectrode 18 a are opposed and which functions effectively as acapacitance element, to the first and second upper-layer wiring layer 30a and 30 b, a distance on the lower electrode side which generally tendsto be longer than a distance on the upper electrode side is madeshorter. Therefore, it is possible to reduce a difference in theirimpedances and suppress an increase of asymmetry in characteristics of acapacitance element. In other words, it is possible to improve symmetryin characteristics of a capacitance element.

A Fifth Embodiment

FIG. 29 is a schematic sectional diagram showing a capacitance elementaccording to a fifth embodiment of the present invention. FIG. 30 andFIG. 31 are schematic sectional process diagrams for explaining a methodof fabricating the capacitance element shown in FIG. 29. Additionally,the same elements as constituent elements of the capacitance elementshown in FIG. 21 to FIG. 28 according to the fourth embodiment aredenoted by the same reference numerals to omit at description thereof.

As shown in FIG. 29, the capacitance element according to thisembodiment is characterized in that, instead of the polysilicon dummylayer 14 for making a level difference in the capacitance element shownin FIG. 20 according to the fourth embodiment, an insulation dummy layermade of SiN, SiO₂ and the like having a predetermined thickness, forexample, a SiO₂ dummy layer 32 for making a level difference made of aSiO₂ layer having a thickness of 100 to 500 nm or so is formed. Theother constituent elements are the same as those in the fourthembodiment.

Next, a method of fabricating the capacitance element shown in FIG. 29with reference to schematic sectional process diagrams of FIG. 30 andFIG. 31.

To start with, as shown in FIG. 30, after the first insulation film 12made of, e.g. a SiO₂ layer is formed on the semiconductor substrate 10,further on the first insulation film 12 is formed an insulation film,e.g. a SiO₂ film up to a thickness of 100 to 500 nm or so. Subsequently,by the photolithographing process and etching process, the SiO₂ film isselectively removed by etching into a predetermined pattern.

In this manner, the SiO₂ dummy layer 32 made of a SiO₂ film having athickness of 100 to 500 nm or so is formed on the periphery ofpredefined area of forming the capacitance element on the semiconductorsubstrate 10 through the first insulation film 12.

Next, as shown in FIG. 31, in the same way as processes shown in FIG. 22to FIG. 28 according to the fourth embodiment, the second insulationfilm 16 is formed on the whole surface of base body including the SiO₂dummy layer 32; the TiN/Al—Si/Ti/TiON/Ti lamination film 18 being formedon the second insulation film 16; the upper electrode 22 being formed onthe TiN/Al—Si/Ti/TiON/Ti lamination film 18 through the dielectric film20; and the TiN/Al—Si/Ti/TiON/Ti lamination film 18 being patterned bythe photolithographing process and RIE process to form the lowerelectrode 18 a having a recess form section in which the surface of itsperiphery situated over the SiO₂ dummy layer 32 lies on a higher levelthan the surface of its center on which the upper electrode 22 isformed.

In this way, the capacitance element comprised of the upper electrode 22and lower electrode 18 a which sandwich the dielectric film 20 betweenthem is formed.

Note that the surface of dielectric film 20 in the capacitance elementat this moment is lower in level than the surface of the periphery oflower electrode 18 a situated over the SiO₂ dummy layer 32.

Subsequently, on the whole surface of base body including the upperelectrode 22 and lower electrode 18 a is piled a SiO₂ film which isfurther coated with a SOG film. Thereafter, these SOG film and SiO₂ filmare etched back for smoothing them to fill the recess of lower electrode18 a with a recess form section and also cover the surface of upperelectrode 22. The smoothing insulation film 24 that smooths the wholesurface of base body is thus formed.

It is noted that, in the smoothing process of the whole surface of basebody, i.e. the forming process of the smoothing insulation film 24, thesurface of dielectric film 20 formed on the center of lower electrode 18a with a recess form section is lower in level than the surface of theperiphery of lower electrode 18 a situated over the SiO₂ dummy layer 32.Under a general smoothing etch-back condition, the difference betweenetching rates of SiO₂ and Ti or TiN is not so large. For this reason,when the SOG film and SiO₂ film are etched back, the periphery of lowerelectrode 18 a acts as an etching stopper. Thus, although the surface ofthe periphery of lower electrode 18 a may be exposed, the surface ofdielectric film 20 will never be exposed by etching.

Subsequently, on the whole surface of base body including the peripheryof lower electrode 18 a and the smoothing insulation film 24 is piledthe insulation film 26 made of, e.g. a SiO₂ film to form the inter-layerinsulation film 27 made of the smoothing insulation film 24 andinsulation film 26. Then, the inter-layer insulation film 27 on upperelectrode 22 is selectively removed by etching and also the inter-layerinsulation film 27 on the periphery of lower electrode 18 a isselectively removed by etching to open the first and second via-holes 28a and 28 b. There may be a case where the TiN layer of the surface oflower electrode 18 a is removed.

Additionally, at this time, a film thickness of the inter-layerinsulation film 27 on upper electrode 22 to be etched for opening thefirst via-hole 28 a is approximately equal to a film thickness of theinter-layer insulation film 26 on the periphery of lower electrode 18 ato be etched for opening the second via-hole 28 b. Therefore, when thesefirst and second via-holes 28 a and 28 b are opened, an excessoveretching to the surface of upper electrode 22 will never happen.

Subsequently, the first and second upper-layer wiring layers 30 a and 30b which are respectively connected to the upper electrode 22 and theperiphery of lower electrode 18 a through the first and second via-holes28 a and 28 b are formed.

As described above, in this embodiment, the SiO₂ dummy layer 32 having apredetermined thickness of, e.g. 100 to 500 nm or so for making a leveldifference is formed on the periphery of predefined area of forming thecapacitance element on the semiconductor substrate 10 through the firstinsulation film 12; the second insulation film 16 being formed on thewhole surface of base body including the SiO₂ dummy layer 32; the lowerelectrode 18 a having a recess form section in which the surface of itsperiphery over the SiO₂ dummy layer 32 lies on a higher level than thesurface of its center being formed; and the upper electrode 22 beingformed on the center through the dielectric film 20 having the surfacewhich is lower than the surface of the periphery of lower electrode 18 aover the SiO₂ dummy layer 32. Therefore, when the SiO₂ film is piled onthe whole surface of base body, further coated with SOG film and thenprocessed to be smoothed by etching back, the periphery of lowerelectrode 18 a acts as an etching stopper and so the dielectric film 20will never sustain damage by etching. Consequently, similarly to thefirst embodiment, it is possible to suppress the fluctuation incharacteristics such as a capacitance value or the like and thedegradation of reliability on a capacitance element, thus allowing acapacitance element having satisfactory characteristics and highreliability to be obtained.

Moreover, when the first and second via-holes 28 a and 28 b are openedin order to form the first and second upper-layer wiring layers 30 a and30 b which are respectively connected to the upper electrode 22 andlower electrode 18 a of the capacitance element a film thickness of theinter-layer insulation film 27 on upper electrode 22 to be etched foropening the first via-hole 28 a is nearly equal to a film thickness ofthe inter-layer insulation film 27 on the periphery of lower electrode18 a to be etched for opening the second via-hole 28 b. For this reason,an excess overetching to the surface of upper electrode 22 will nevertake place and so the upper electrode 22 and the dielectric film 20thereunder will never suffer damage. Therefore, just as in the firstembodiment, it is possible to further suppress the fluctuation incharacteristics such as a capacitance value or the like and thedeterioration of reliability on a capacitance element thereby allowing acapacitance element having better characteristics and a higherreliability to be obtained.

Furthermore, the depth of the second via-hole 28 b opened on the lowerelectrode 18 a is approximately equal to the depth of the first via-hole28 a opened on the upper electrode 22. Thus, of distances from the areawhere the upper electrode 22 and lower electrode 18 a are opposed andwhich functions effectively as a capacitance element to the first andsecond upper-layer wiring layers 30 a and 30 b, a distance on the lowerelectrode side which generally tends to be longer than that on the upperelectrode side is made shorter. Therefore, similarly to the firstembodiment, it is possible to reduce the difference between theirimpedances and suppress an increase of asymmetry in characteristics of acapacitance element, thus enabling symmetry in characteristics of acapacitance element to be improved.

Additionally, the above described fifth embodiment has the SiO₂ dummylayer 32 having a predetermined thickness of, e.g. 100 to 500 nm or sofor making a level difference formed on the periphery of predefined areaof forming a capacitance element on the semiconductor substrate 10through the first insulation film 12.

However, instead of forming such a SiO₂ dummy layer 32, the firstinsulation layer 12 in the center of a predefined area of forming acapacitance element on the semiconductor substrate 10 may selectively beremoved by etching through the photolithographing process and etchingprocess to form a recess about 100 to 500 nm deep. In addition, theselective etching of the first insulation layer 12 may be combined withthe dummy layer 32(or dummy layer 14 or dummy layer 34 described belowto form a final dummy layer, whereby the recess about 100 to 500 nm indepth can also be formed.

In any of these cases, it will be possible to form the second insulationfilm 16 on the first insulation film 12 in which the recess about 100 to500 nm deep is formed in the center of the predefined area of formingthe capacitance element, in the same way as in the second embodiment;form the TiN/Al—Si/Ti/TiON/Ti lamination film 18 on the secondinsulation film 16; and pattern the TiN/Al—Si/Ti/TiON/Ti lamination film18 to form the lower electrode 18 a having a recess form section inwhich the surface of its periphery lies on a higher level than thesurface of its center located above the recess formed on the firstinsulation film 12. Therefore, the same effect as in the above fifthembodiment can be achieved.

A Sixth Embodiment

FIG. 32 is a schematic sectional diagram showing a capacitance elementaccording to a sixth embodiment of the present invention. FIG. 33 toFIG. 38 are each a schematic sectional process diagram for explaining amethod of fabricating the capacitance element shown in FIG. 32. It isnoted herein that the same elements as constituent elements of thecapacitance element shown in FIG. 20 to FIG. 28 according to the fourthembodiment are denoted by the same reference numerals to omit adescription thereof.

As shown in FIG. 32, the capacitance element according to thisembodiment is characterized in that, as compared with the capacitanceelement shown in FIG. 20 according to the fourth embodiment, instead ofthe polysilicon dummy layer 14 formed on the periphery of thecapacitance element for making a level difference a polysilicon dummylayer 34 having the same thickness of, e.g. 100 to 500 nm or so formaking a level difference is formed on the periphery of the capacitanceelement.

Moreover, it is also characterized in that, instead of the lowerelectrode 18 a made of, e.g. TiN/Al—Si/Ti/TiON/Ti and having a recessform section shown in FIG. 20 according to the fourth embodiment, a flatlower electrode 18 b made of, e.g. TiN/Al—Si/Ti/TiON/Ti is formed andalso, separately from the lower electrode 18 b, a dummy electrode 18 cmade of, e.g. TiN/Al—Si/Ti/TiON/Ti having a higher surface than that ofthe upper electrode 22 is formed over the polysilicon dummy layer 34 formaking a level difference surrounding the capacitance element.

The other components are approximately the same as those of the fourthembodiment.

Next, a method of fabricating the capacitance element shown in FIG. 32will be described with reference to schematic sectional process diagramsof FIG. 32 to FIG. 38.

To begin with, as shown in FIG. 33, after the first insulation film 12made of, e.g. a SiO₂ film is formed on the semiconductor substrate 10, apolysilicon layer is formed further on the first insulation film 12 upto a predetermined thickness of, e.g. 100 to 500 nm or so.

Subsequently, through the photolithographing process and RIE process,the polysilicon layer is selectively removed by etching into apredetermined pattern.

In this way, a polysilicon dummy layer 34 made of a polysilicon layerhaving a thickness of 100 to 500 nm or so for making a level differenceis formed on the periphery of a predefined area of forming thecapacitance element on the semiconductor substrate 10 through the firstinsulation film 12.

Additionally, the forming process of the polysilicon dummy layer 34 canbe combined with a forming process of a polysilicon layer used as a gateelectrode of the other element, e.g. MOSTr, a resistance layer of aresistance element or an electrode of BipTr in LSI.

Next, as shown in FIG. 34, in the same way as processes shown in FIG. 22to FIG. 24 according to the fourth embodiment, the second insulationfilm 16 is formed on the whole surface of base body including thepolysilicon dummy layer 34 for making a level difference. Thisinsulation film 16 can be dispensed with. Then, on the second insulationfilm 16 is formed a TiN/Al—Si/Ti/TiON/Ti lamination film or a layeredfilm of Cu, Al—Cu and the like, in this embodiment aTiN/Al—Si/Ti/TiON/Ti lamination film 18. On this TiN/Al—Si/Ti/TiON/Tilamination film 18 is formed an upper electrode 22 made of a Ti film, aTiN film or a Ti/TiN layered film through a dielectric film 20 of Ta₂O₅,SiO₂, SiN or the like, in this embodiment Ta₂O₅.

Note that the surface of the dielectric film 20 at this moment is lowerin height than the top surface of the TiN/Al—Si/Ti/TiON/Ti laminationfilm 18 located over the polysilicon dummy layer 34.

Next, as shown in FIG. 35, through the photolithographing process andRIE process, the TiN/Al—Si/Ti/TiON/Ti lamination film 18 is selectivelyremoved by etching into a predetermined pattern.

In this manner, the lower electrode 18 b made of TiN/Al—Si/Ti/TiON/Ti isformed in the predefined area of forming the capacitance element on thesecond insulation film 16 and also, separately from the lower electrode18 b, the dummy electrode 18 c of TiN/Al—Si/Ti/TiON/Ti having the topsurface higher than the surface of lower electrode 18 b is formed overthe polysilicon dummy layer 34 surrounding the predefined area offorming the capacitance element.

Simultaneously with the formation of lower electrode 18 b, lower-layerwiring layers (not shown) made of a TiN/Al—Si/Ti/TiON/Ti lamination filmof other elements in LSI are formed.

The capacitance element is thus formed, which is comprised of the upperelectrode 22 and lower electrode 18 b sandwiching the dielectric film 20between them.

Note that the surface of the dielectric film 20 at this time is lower inheight than the top surface of the dummy electrode 18 c surrounding thepredefined area of forming the capacitance element and located over thepolysilicon dummy layer 34.

Next, as shown in FIG. 36, on the whole surface of base body includingthe upper electrode 22 and lower electrode 18 b is piled a SiO₂ film upto a thickness of 300 to 1500 nm or so. This SiO₂ film is further coatedwith a SOG film. Thereafter, there SOG film and SiO₂ film are processedto be smoothed by etching back.

In this way, the recess surrounded by the dummy electrode 18 c is filledand smoothed to form the smoothing insulation film 24.

In this process of smoothing the whole surface of base body, namely, theprocess of forming the smoothing insulation film 24, the surface ofdielectric film 20 formed on the lower electrode 18 b is lower in levelthan the top surface of dummy electrode 18 c surrounding the predefinedarea of forming the capacitance element and located over the polysilicondummy layer 34, Under a normal etch-back condition, there is not a largedifference between an etching rate of Ti or TiN and that of SiO₂. Thus,when the SOG film and SiO₂ film are etched back, the surface ofdielectric film 20 will never be exposed by etching.

Next, as shown in FIG. 37, using the plasma CVD method for example, onthe whole surface of base body including the dummy electrode 18 c andsmoothing insulation film 24 is piled the insulation film 26. Thesmoothing insulation film 24 and insulation film 26 make the inter-layerinsulation film 27 together.

Subsequently, using the photolithographing process and dry etchingmethod, the inter-layer insulation film 27 on the upper electrode 22 andlower electrode 18 b is selectively removed by etching to open the firstand second via-holes 28 a and 28 b.

Next, as shown in FIG. 38, after an Al-alloy layer is piled using thesputtering method for example the Al-alloy layer is processed using thephotolithographing process and dry etching method to form the first andsecond upper-layer wiring layers 30 a and 30 c made of Al-alloy layerand each connected to the upper electrode 22 and the periphery of lowerelectrode 18 b through the first and second via-holes 28 a and 28 c.

Simultaneously with the formation of the first and second upper-layerwiring layers 30 a and 30 c, upper layer wiring layers (not shown) ofother elements in LSI are formed.

As described above, in this embodiment, the polysilicon dummy layer 34having a thickness of about 100 to 500 nm for making a level differenceis formed on the periphery of a predefined area of forming thecapacitance element on the semiconductor substrate 10 through the firstinsulation film 12; the lamination film 18 of, e.g. TiN/Al—Si/Ti/TiON/Tibeing formed on the whole surface of base body including the polysilicondummy layer 34 through the second insulation film 16 and patterned intoa predetermined shape; the lower electrode 18 b of TiN/Al—Si/Ti/TiON/Tibeing formed in the predefined area of forming the capacitance element;the dummy electrode 18 c of TiN/Al—Si/Ti/TiON/Ti having the surfacehigher than the surface of lower electrode 18 b being formed above thepolysilicon dummy layer 34 surrounding the lower electrode 18 b; theupper electrode 22 being formed on the lower electrode 18 b through thedielectric film 20; and the surface of dielectric film 20 is made lowerin height than the top surface of dummy electrode 18 c formed above thepolysilicon dummy layer 34. Thus, when the smoothing process isperformed by etching back after a SiO₂ film is piled on the wholesurface of base body and further coated with a SOG film, the dummyelectrode 18 c acts as an etching stopper and so the dielectric film 20under the upper electrode 22 will never sustain damage by etching.Therefore, similarly to the fourth embodiment, it is possible tosuppress the fluctuation in characteristics, such as a capacitance valueor the like and the deterioration of reliability on a capacitanceelement, thereby allowing a capacitance element having satisfactorycharacteristics and high reliability to be obtained.

Additionally, in the fourth to sixth embodiments, there is described thecase where the lower electrode 18 a or 18 b is connected to the secondupper-layer wiring layer 30 b or 30 c through the second via-hole 28 bor 28 c. However, there may be a case where the lower electrode 18 a or18 b also serves as a wiring layer intactly and is connected to anotherelement of LSI.

In this case, it is unnecessary to selectively remove the inter-layerinsulation film 27 on the lower electrode 18 a or 18 b by etching so asto open the second via-hole 28 b or 28 c.

Moreover, in order to form the first and second upper-layer wiringlayers 30 a, 30 b and 30 c, the following method can be employed insteadof piling the Al-alloy layer and processing the same. After aW(tungsten) layer is piled using the CVD method, W plugs whichrespectively fill the first and second via-holes 28 a, 28 b and 28 c areformed by etching back. Further, using the sputtering method is piled anAl-alloy layer. Thereafter, the Al-alloy layer is processed to form thefirst and second upper-layer wiring layers which are connected to the Wplugs inside the first and second via-holes 28 a 28 b and 28 c,respectively.

What is claimed is:
 1. A semiconductor device characterized bycomprising: a lower electrode that is formed on a semiconductorsubstrate through a first insulation film and has a recess form sectionin which the surface of its periphery lies on a higher level than thesurface of its center; an upper electrode that is formed on the centerof the lower electrode through a dielectric film, the surface of whichlies on a lower level than the surface of the periphery of the lowerelectrode; and a second insulation film that fills a recess of the lowerelectrode having the recess form section.
 2. A semiconductor deviceaccording to claim 1, characterized in that: a third insulation film isformed on the periphery of the lower electrode, the upper electrode andthe second insulation film to make an inter-layer insulation film; afirst wiring layer that is connected to the upper electrode through afirst via-hole opened in the inter-layer insulation film; and a secondwiring layer that is connected to the periphery of the lower electrodethrough a second via-hole opened in the inter-layer insulation film. 3.A semiconductor device according to claim 1, characterized in that adummy layer provided below the periphery of the lower electrode formaking a level difference is formed out of a layer of the same materialas that of an electrode or a resistance layer of another element.
 4. Asemiconductor device according to claim 2, characterized in that a dummylayer provided below the periphery of the lower electrode for making alevel difference is formed out of a layer of the same material as thatof an electrode or a resistance layer of another element.
 5. Asemiconductor device characterized by comprising: a lower electrodeformed on a semiconductor substrate through a first insulation film; adummy electrode having the surface higher than the surface of the lowerelectrode; an upper electrode formed on the lower electrode through adielectric film, the surface of which lies on a level lower than the topsurface of the dummy electrode; and a second insulation film that fillsa recess surrounded by the dummy electrode.
 6. A semiconductor deviceaccording to claim 5, characterized in that: a third insulation film isformed on the dummy electrode, the upper electrode and the secondinsulation film to make an inter-layer insulation film; a first wiringlayer that is connected to the upper electrode through a first via-holeopened in the inter-layer insulation film; and a second wiring layerthat is connected to the lower electrode through a second via-holeopened in the inter-layer insulation film.
 7. A semiconductor deviceaccording to claim 5, characterized in that a dummy layer provided belowthe dummy electrode for making a level difference is formed out of alayer of the same material as that of an electrode or a resistance layerof another element.
 8. A semiconductor device according to claim 5,characterized in that a dummy layer provided below the dummy electrodefor making a level difference is formed out of a layer of the samematerial as that of an electrode or a resistance layer of anotherelement.
 9. A semiconductor device characterized by comprising: a lowerelectrode that is formed on a semiconductor substrate through a firstinsulation film and has a recess form section in which the surface ofits periphery lies on a level higher than the surface of its center; anupper electrode that is formed on the center of the lower electrodethrough a dielectric film and has the surface lower in level than thesurface of the periphery of the lower electrode; and a second insulationfilm that fills a recess of the lower electrode having a recess formsection and also covers the surface of the upper electrode.
 10. Asemiconductor device according to claim 9, characterized in that: athird insulation film is formed on the periphery of the lower electrodeand the second insulation film to make an inter-layer insulation film; afirst wiring layer that is connected to the upper electrode through afirst via-hole opened in the inter-layer insulation film; and a secondwiring layer that is connected to the periphery of the lower electrodethrough a second via-hole opened in the inter-layer insulation film. 11.A semiconductor device according to claim 9, characterized in that adummy layer provided below the periphery of the lower electrode formaking a level difference is formed out of a layer of the same materialas that of an electrode or a resistance layer of another element.
 12. Asemiconductor device according to claim 10, characterized in that adummy layer provided below the periphery of the lower electrode formaking a level difference is formed out of a layer of the same materialas that of an electrode or a resistance layer of another element.
 13. Asemiconductor device characterized by comprising: a lower electrodeformed on a semiconductor substrate through a first insulation film; adummy electrode that is formed on the periphery of the lower electrodeand has the surface higher in level than the surface of the lowerelectrode; an upper electrode that is formed on the lower electrodethrough a dielectric film and has the surface lower in level than thetop surface of the dummy electrode; and a second insulation film thatfills a recess surrounded by the dummy electrode and also covers thesurface of the lower electrode and upper electrode.
 14. A semiconductordevice according to claim 13, characterized in that: a third insulationfilm is formed on the dummy electrode, the upper electrode and thesecond insulation film to make an inter-layer insulation film; a firstwiring layer that is connected to the upper electrode through a firstvia-hole opened in the inter-layer insulation film; and a second wiringlayer that is connected to the lower electrode through a second via-holeopened in the inter-layer insulation film.
 15. A semiconductor deviceaccording to claim 13, characterized in that the dummy layer providedbelow the dummy electrode for making a level difference is formed out ofa layer of the same material as that of an electrode or a resistancelayer of another element.
 16. A semiconductor device according to claim14, characterized in that the dummy layer provided below the dummyelectrode for making a level difference is formed out of a layer of thesame material as that of an electrode or a resistance layer of anotherelement.
 17. A method of fabricating a semiconductor devicecharacterized by comprising the steps of: forming a dummy layer having apredetermined thickness for making a level difference on the peripheryof a predefined area of forming a capacitance element on a semiconductorsubstrate through a first insulation film; forming a lower electrodethat has a recess form section in which the surface of its peripherylies on a level higher than the surface of its center, on the predefinedarea of forming the capacitance element, by piling a conductor film onthe first insulation film and the dummy layer and then patterning theconductor film; forming an upper electrode on the center of the lowerelectrode through a dielectric film, the surface of which lies on alevel lower than the surface of the periphery of the lower electrode;and forming a second insulation film on the whole surface of a base bodyto fill a recess of the lower electrode having the recess form section.18. A method of fabricating a semiconductor device according to claim17, characterized by further comprising the steps of: forming a thirdinsulation film on the whole surface of the base body including theperiphery of the lower electrode, the upper electrode and the secondinsulation film to make an inter-layer insulation film; opening a firstvia-hole in the inter-layer insulation film on the upper electrode andalso opening a second via-hole in the inter-layer insulation film on theperiphery of the lower electrode; and forming a first wiring layer thatis connected to the upper electrode through the first via-hole and alsoforming a second wiring layer that is connected to the periphery of thelower electrode through the second via-hole.
 19. A method of fabricatinga semiconductor device according to claim 17, characterized in that thestep of forming the dummy layer for making a level difference iscombined with a step of forming an electrode or a resistance layer ofanother element.
 20. A method of fabricating a semiconductor deviceaccording to claim 18, characterized in that the step of forming thedummy layer for making a level difference is combined with a step offorming an electrode or a resistance layer of another element.
 21. Amethod of fabricating a semiconductor device characterized by comprisingthe steps of: forming a dummy layer having a predetermined thickness formaking a level difference, around a predefined area of forming acapacitance element on a semiconductor substrate through a firstinsulation film; forming a lower electrode in the predefined area offorming a capacitance element by piling a conductor film on the firstinsulation film and the dummy layer, thereafter patterning the conductorfilm, and also forming a dummy electrode that covers the dummy layer andhas the surface higher than the surface of the lower electrode, aroundthe predefined area of forming a capacitance element; forming an upperelectrode on the lower electrode through a dielectric film, the surfaceof which lies on a level lower than the top surface of the dummyelectrode; and forming a second insulation film on the whole surface ofa base body to fill a recess surrounded by the dummy electrode.
 22. Amethod of fabricating a semiconductor device according to claim 21,characterized by further comprising the steps of: forming a thirdinsulation film on the whole surface of the base body including thedummy electrode, the upper electrode and the second insulation film tomake an inter-layer insulation film; opening a first via-hole in theinter-layer insulation film on the upper electrode and also opening asecond via-hole in the inter-layer insulation film on the lowerelectrode; and forming a first wiring layer that is connected to theupper electrode through the first via-hole and also forming a secondwiring layer that is connected to the lower electrode through the secondvia-hole.
 23. A method of fabricating a semiconductor device accordingto claim 21, characterized in that the step of forming the dummy layerfor making a level difference is combined with a step of forming anelectrode or a resistance layer of another element.
 24. A method offabricating a semiconductor device according to claim 22, characterizedin that the step of forming the dummy layer for making a leveldifference is combined with a step of forming an electrode or aresistance layer of another element.
 25. A method of fabricating asemiconductor device characterized by comprising the steps of: forming adummy layer having a predetermined thickness for making a leveldifference on the periphery of a predefined area of forming acapacitance element on a semiconductor substrate through a firstinsulation film; forming a lower electrode having a recess form sectionin which the surface of its periphery lies on a level higher than thesurface of its center, in a predefined area of forming a capacitanceelement, by piling a conductor film on the first insulation film and thedummy layer and then patterning the conductor film; foaming an upperelectrode, the surface of which lies on a level lower than the surfaceof the periphery of the lower electrode, on the center of the lowerelectrode through a dielectric film; and forming a second insulationfilm on the whole surface of a base body to fill a recess of the lowerelectrode having a recess form section and also cover the surface of theupper electrode.
 26. A method of fabricating a semiconductor deviceaccording to claim 25, characterized by further comprising the steps of:forming a third insulation film on the whole surface of the base bodyincluding the periphery of the lower electrode and the second insulationfilm to make an inter-layer insulation film; opening a first via-hole inthe inter layer insulation film on the upper electrode and also openinga second via-hole in the inter-layer insulation film on the periphery ofthe lower electrode; and forming a first wiring layer that is connectedto the upper electrode through the first via-hole and also forming asecond wiring layer that is connected to the periphery of the lowerelectrode through the second via-hole.
 27. A method of fabricating asemiconductor device according to claim 25, characterized in that thestep of forming the dummy layer for making a level difference iscombined with a step of forming an electrode or a resistance layer ofanother element.
 28. A method of fabricating a semiconductor deviceaccording to claim 26, characterized in that the step of forming thedummy layer for making a level difference is combined with a step offorming an electrode or a resistance layer of another element.
 29. Amethod of fabricating a semiconductor device characterized by comprisingthe steps of: forming a dummy layer having a predetermined thickness formaking a level difference around a predefined area of forming acapacitance element on a semiconductor substrate through a firstinsulation film; forming a lower electrode in the predefined area offorming a capacitance element by piling a conductor film on the firstinsulation film and the dummy layer, thereafter patterning the conductorfilm, and also forming a dummy electrode that covers the dummy layer andhas the surface higher than the surface of the lower electrode, aroundthe predefined area of forming a capacitance element; forming an upperelectrode, the surface of which lies on a level lower than the topsurface of the dummy electrode, on the lower electrode through adielectric film; and forming a second insulation film on the wholesurface of a base body to fill a recess surrounded by the dummyelectrode and also cover the surface of the lower electrode and upperelectrode.
 30. A method of fabricating a semiconductor device accordingto claim 29, characterized by further comprising the steps of: forming athird insulation film on the whole surface of the base body includingthe dummy electrode and the second insulation film to make aninter-layer insulation film opening a first via-hole in the inter-layerinsulation film on the upper electrode and also opening a secondvia-hole in the inter-layer insulation film on the lower electrode; andforming a first wiring layer that is connected to the upper electrodethrough the first via-hole and also forming a second wiring layer thatis connected to the lower electrode through the second via-hole.
 31. Amethod of fabricating a semiconductor device according to claim 29,characterized in that the step of forming the dummy layer for making alevel difference is combined with a step of an electrode and aresistance layer of another element.
 32. A method of fabricating asemiconductor device according to claim 30, characterized in that thestep of forming the dummy layer for making a level difference iscombined with a step of forming an electrode or a resistance layer ofanother element.